WCH CH32V003 Series Reference Manual page 59

CH32V003 Reference Manual
PA12
Reserved
_RM
Bit Name
[31:27] Reserved
[26:24] SWCFG
23 TIM1_IREMAP
22 I2C1REMAP1
21 USART1_RM1
[20:19] Reserved
ADC_ETRGREG_R
18
M
ADC_ETRGINJ_R
17
M
16 Reserved
15 PA12_RM
[14:10] Reserved
[9:8] TIM2RM
V1.3
TIM2RM[1:0] TIM1RM[1:0]
Access
RO Reserved
These bits are used to configure the I/O ports for
SW function and trace function. SWD (SDI) is the
debug interface to access the core. It is always
used as a SWD port after system reset.
WO
0xx: SWD (SDI) enabled.
100: Turn off SWD (SDI), which functions as a
GPIO.
Others: Invalid.
Control timer 1 channel 1 selection
RW 0: Select external pins
1: Select internal LSI clock
I2C1 remapping high bit (used in conjunction with
AFIO_PCFR1 register bit1 I2C1_RM [22,1]).
RW 00: default mapping (SCL/PC2, SDA/PC1).
01: Remapping (SCL/ PD1, SDA/ PD0).
1X: Remapping (SCL/PC5, SDA/PC6)
USART1 mapping configuration high (used in
conjunction with AFIO PCFR1 register bit2
USART1RM [21,2]).
00: default mapping (CK/PD4, TX/PD5, RX/PD6,
CTS/PD3, RTS/PC2, SW_RX/PD5).
RW 01: Remapping (CK/PD7, TX/PD0, RX/PD1,
CTS/PC3, RTS/PC2, SW_RX/PD0).
10: Remapping (CK/PD7, TX/PD6, RX/PD5,
CTS/PC6, RTS/PC7, SW_RX/PD6).
11: Remapping (CK/PC5, TX/PC0, RX/PC1,
CTS/PC6, RTS/PC7, SW_RX/PC0).
RO Reserved
Remap bit for ADC external trigger rule
conversion.
0: ADC external trigger rule conversion connected
RW
to PD3.
1: ADC external trigger rule conversion connected
to PC2.
Remap bit for ADC external trigger rule
conversion.
0: ADC external trigger rule conversion connected
RW
to PD3.
1: ADC external trigger rule conversion connected
to PC2.
RO Reserved
Pin PA1 & PA2 remapping bit, this bit can be read
or written by user. It controls the proper function
of PA1 and PA2 (set to 1 when connected to an
RW
external crystal pin)
0: Pin is used as GPIO and multiplexed function
1: No functional role for pins
RO Reserved
Remap bits for timer 2. These bits can be read and
written by the user. It controls the mapping of
RW
Timer 2's channels 1 through 4 and external trigger
(ETR) on the GPIO ports.
59
Reserved
Description
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USAR
I2C1 SPI1
T1_
RM RM
RM
Reset value
0
0
0
0
0
0
0
0
0
0
0
0