I2C Data Register (I2C_Datar); I2C Status Register - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[14:10] Reserved
[9:8] ADD9_8
[7:1] ADD7_1
0 ADD0
13.11.4 I2C Own address register 2(I2C1_OAR2)
Offset address: 0x0C
15 14 13 12
Reserved
Bit Name
[15:8] Reserved
[7:1] ADD2
0 ENDUAL

13.11.5 I2C Data register (I2C_DATAR)

Offset address: 0x10
15 14 13 12
Reserved
Bit Name
15:8 Reserved
7:0 DR
13.11.6 I2C Status register 1(I2C_STAR1)
Offset address: 0x14
15 14 13 12
PECE
Reserved
RR
Bit Name
[15:13] Reserved
12 PECERR
11 OVR
V1.3
0: 7-bit slave address (does not respond to 10-bit
address)
RO Reserved
Interface address, bits 9-8 when using a 10-bit
RW
address, ignored when using a 7-bit address.
RW Interface address, bits 7-1.
Interface address, bit 0 when using a 10-bit
RW
address, ignored when using a 7-bit address.
11 10 9 8
Access
RO Reserved
Interface address, bits 7-1 of the address in dual
RW
address mode.
Dual address mode enable bit, set this bit to allow
RW
ADD2 to be recognized as well.
11 10 9 8
Access
RO Reserved
Data register, this field is used to store the received
RW
data or to store the data used to send to the bus.
11 10 9 8
ARL BER
OVR AF
O R
Access
RO Reserved
The PEC error flag bit occurs on reception, and
this bit can be reset by a user write of 0 or by
hardware when PE goes low.
RW0
1: There is a PEC error and the PEC is received
and NAK is returned.
0: No PEC error.
Overrun and underrun flag bits.
1: There are overrun and underrun events
RW0 occurring: when NOSTRETCH=1, when a new
byte is received in receive mode, the content in the
data register has not been read out, then the newly
7 6 5
ADD2[7:1]
Description
7 6 5
Description
7 6 5
Reser STOP
TxE RxNE
ved
Description
153
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0
0
0
0
4 3 2 1
Reset value
0
0
0
4 3 2 1
DR[7:0]
Reset value
0
0
4 3 2 1
ADD ADD
BTF
F 10 R
Reset value
0
0
0
0
ENDU
AL
0
0
SB