Spi Control Register 2 (Spi1_Ctlr2) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
12 CRCNEXT
11 DFF
10 RXONLY
9 SSM
8 SSI
7 Reserved
6 SPE
[5:3] BR
2 MSTR
1 CPOL
0 CPHA

14.3.2 SPI Control register 2 (SPI1_CTLR2)

Offset address: 0x04
15 14 13 12
Reserved
V1.3
mode.
1: Initiate CRC calculation.
0: CRC calculation is disabled.
After the next data transfer, send the value of the
CRC register. This should be set immediately after
RW the last data is written to the data register.
1: Sending CRC checksum results.
0: Continue to send data from the data register.
Data frame format bit, this bit can only be written
when SPE is 0.
RW
1: Sending and receiving using 16-bit data length.
0: Use 8-bit data length for sending and receiving.
The receive-only bit in two-wire mode is used in
conjunction with BIDIMODE. Setting this bit
RW allows the device to receive only and not transmit.
1: Receive only, simplex mode.
0: Full-duplex mode.
Software
determines whether the level of the NSS pin is
RW controlled by hardware or software.
1: Software control of the NSS pins.
0: Hardware control NSS pins.
Internal slave select bit, with SSM set, this bit
determines the level of the NSS pin.
RW
1: NSS is high.
0: NSS is low.
RO Reserved
SPI enable bit.
RW 1: Enable SPI.
0: Disable SPI.
Baud rate setting field, this field cannot be
modified during communication.
000: FPCLK /2; 001: FPCLK /4.
RW
010: FPCLK /8; 011: FPCLK /16.
100: FPCLK /32; 101: FPCLK /64.
110: FPCLK /128; 111: FPCLK /256.
Master-slave setting bit, this bit cannot be
modified during communication.
RW
1: Configured as a master device.
0: Configured as a slave device.
Clock polarity selection bit, this bit cannot be
modified during communication.
RW
1: SCK is held high in idle state.
0: SCK is held low in idle state.
Clock phase setting bit, this bit cannot be modified
during communication.
RW 1: Data sampling starts from the second clock
edge.
0: Data sampling starts from the first clock edge.
11 10 9 8
slave management
7 6 5
RXN
TXEI ERRI
E
E E
IE
161
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0
0
0
bit, this bit
0
0
0
0
0
0b
0
0
4 3 2 1
TXD
Reserved SSOE MA
EN
0
RXD
MA
EN