WCH CH32V003 Series Reference Manual page 18

CH32V003 Reference Manual
25 PLLRDY
24 PLLON
[23:20] Reserved
19 CSSON
18 HSEBYP
17 HSERDY
16 HSEON
[15:8] HSICAL
[7:3] HSITRIM
2 Reserved
1 HSIRDY
0 HSION
V1.3
PLL clock-ready lock flag bit.
RO 1: PLL clock lock.
0: PLL clock is not locked.
PLL clock enable control bit.
1: Enables the PLL clock.
RW 0: Turn off the PLL clock.
Note: After entering Standby low-power mode, this bit is
cleared by hardware to 0.
RO Reserved
Clock security system enable control bit.
1: Enable the clock security system. When HSE is ready
(HSERDY set to 1), the hardware turns on the clock
monitoring function of HSE and triggers CSSF flag and
RW
NMI interrupt when HSE is found to be abnormal; when
HSE is not ready, the hardware turns off the clock
monitoring function of HSE.
0: Turns off the clock security system.
External high-speed crystal bypass control bit.
1: Bypass external high-speed crystal/ceramic resonators
(using an external clock source).
RW
0: No bypass of high-speed external crystal/ceramic
resonators.
Note: This bit needs to be written with HSEON at 0.
External high-speed crystal oscillation stabilization ready
flag bit (set by hardware).
1: Stable external high-speed crystal oscillation.
RO
0: External high-speed crystal oscillation is not stabilized.
Note: After the HSEON bit is cleared to 0, it takes 6 HSE
cycles for this bit to clear to 0.
External high-speed crystal oscillation enable control bit.
1: Enables the HSE oscillator.
RW 0: Turn off the HSE oscillator.
Note: This bit is cleared to 0 by hardware after entering
Standby low-power mode.
Internal high-speed clock calibration values, which are
RO
automatically initialized at system startup.
Internal high-speed clock adjustment value.
The user can enter an adjustment value to superimpose on
the HSICAL[7:0] value to adjust the frequency of the
internal HSI RC oscillator based on voltage and
RW
temperature variations.
The default value is 16, which can adjust the HSI to
24MHz ±1%; the change of HSICAL is adjusted about
60KHz per step.
RO Reserved
Internal high-speed clock (24MHz) Stable Ready flag bit
(set by hardware).
1: Stable internal high-speed clock (24MHz).
RO
0: The internal high-speed clock (24MHz) is not stable.
Note: After the HSION bit is cleared to 0, it takes 6 HSI
cycles for the bit to be cleared to 0.
Internal high-speed clock (24MHz) enable control bit.
1: Enables the HSI oscillator.
0: Turn off the HSI oscillator.
RW Note: This bit is set to 1 by hardware to start the internal
24MHz RC oscillator when returning from standby mode
or when the external oscillator HSE used as the system
clock fails.
17
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0
0
0
0
0
0
0
xxh
10000
0
1
1