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CH32V003 Reference Manual
A precision external low frequency 128KHz crystal LSI can be selected as the auto-wakeup count time base.
2.4 Register description
Name
R32_PWR_CTLR
R32_PWR_CSR
R32_PWR_AWUCSR
R32_PWR_AWUWR
R32_PWR_AWUPSC
2.4.1 Power control register (PWR_CTLR)
Offset address: 0x00
31
30
29
28
15
14
13
12
Reserved
Bit
Name
[31:8]
Reserved
[7:5]
PLS[2:0]
4
PVDE
[3:2]
Reserved
1
PDDS
0
Reserved
2.4.2 Power control/status register (PWR_CSR)
Offset address: 0x04
31
30
29
28
15
14
13
12
V1.3
Table 2-2 PWR-related registers list
Access address
0x40007000
Power control register
0x40007004
Power control/status register
0x40007008
Auto-wakeup control/status register
Auto-wakeup window comparison
0x4000700C
value register
0x40007010
Auto-wakeup crossover factor register
27
26
25
24
Reserved
11
10
9
8
Access
RO
Reserved
PVD voltage monitoring threshold setting. See the
Electrical Characteristics section of the datasheet for
detailed instructions.
000: 2.85V rising edge/2.7V falling edge.
001: 3.05V rising edge/2.9V falling edge.
RW
010: 3.3V rising edge/3.15V falling edge.
011: 3.5V rising edge/3.3V falling edge.
100: 3.7V rising edge/3.5V falling edge.
101: 3.9V rising edge/3.7V falling edge.
110: 4.1V rising edge/3.9V falling edge.
111: 4.4V rising edge/4.2V falling edge.
Power supply voltage monitoring function enable flag bit
RW
1: Enable the power supply voltage monitoring function.
0: Disable the power supply voltage monitoring function.
RO
Reserved
Standby/ Sleep mode selection bit in power-down deep
sleep scenario.
RW
1: Enter Standby mode.
0: Enter Sleep mode.
RO
Reserved
27
26
25
24
Reserved
11
10
9
8
Reserved
Description
23
22
21
20
7
6
5
4
PLS[2:0]
PVDE Reserved PDDS Reserved
Description
23
22
21
20
7
6
5
8
http://wch.cn
Reset value
0x00000000
0x00000000
0x00000000
0x0000003f
0x00000000
19
18
17
3
2
1
Reset
value
19
18
17
4
3
2
1
PVD0
Reserved
16
0
0
0
0
0
0
0
16
0
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