Apb1 Peripheral Clock Enable Register; Control/Status Register - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
3.4.8 APB1 Peripheral clock enable register (RCC_APB1PCENR)
Offset address: 0x1C
31 30 29 28
PWR
Reserved
EN
15 14 13 12
Reserved
Bit Name
[31:29] Reserved
28 PWREN
[27:22] Reserved
21 I2C1EN
[20:12] Reserved
11 WWDGEN
[10:1] Reserved
0 TIM2EN
Note: When the peripheral clock is not enabled, the software cannot read out the peripheral register value and
the value returned is always 0.
3.4.9 Control/Status register (RCC_RSTSCKR)
Offset address: 0x24
31 30 29 28
LPW WW IWD
SFT
R DG G
RSTF
RSTF RSTF RSTF
15 14 13 12
Bit Name
31 LPWRRSTF
30 WWDGRSTF
29 IWDGRSTF
V1.3
27 26 25 24
Reserved
11 10 9 8
WW
DG
EN
Access
RO Reserved
Power interface module clock enable bit.
RW
1: Module clock is on; 0: Module clock is off.
RO Reserved
I2C 1 interface clock enable bit.
RW
1: Module clock is on; 0: Module clock is off.
RO Reserved
Window watchdog clock enable bit.
RW
1: Module clock is on; 0: Module clock is off.
RO Reserved
Timer 2 module clock enable bit.
RW
1: Module clock is on; 0: Module clock is off.
27 26 25 24
POR PIN Reser RMV
RSTF RSTF ved F
11 10 9 8
Reserved
Access
Low-power reset flag.
1: Occurrence of low-power resets.
RO 0: No low-power reset occurs.
Set to 1 by hardware when a low-power management reset
occurs; cleared by software writing of the RMVF bit.
Window watchdog reset flag.
1: Occurrence of a window watchdog reset.
RO 0: No window watchdog reset occurs.
Set to 1 by hardware when a window watchdog reset
occurs; cleared by software writing of the RMVF bit.
Independent watchdog reset flag.
1: Occurrence of an independent watchdog reset.
RO
0: No independent watchdog reset occurs.
Set to 1 by hardware when an independent watchdog reset
23 22 21
I2C1
EN
7 6 5
Reserved
Description
23 22 21 20
7 6 5 4
Description
23
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20 19 18 17
Reserved
4 3 2 1
Reset
value
19 18 17
Reserved
3 2 1
LSI
RDY
Reset
value
16
0
TIM2
EN
0
0
0
0
0
0
0
0
16
0
LSION
0
0
0