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CH32V003 Reference Manual
10.3.3 Forced output mode
The output pattern of the timer's compare capture channel can be forced by software to output a determined
level without relying on comparison of the compare capture register's shadow register with the core counter.
This is done by setting OCxM to 100b, which forces OCxREF to low, or by setting OCxM to 101b, which
forces OCxREF to high.
Note that by forcing OCxM to 100b or 101b, the comparison process of the internal core counters and compare
capture registers is still going on, the corresponding flags are still set, and interrupts and DMA requests are
still being generated.
10.3.4 PWM input mode
The PWM input mode is used to measure the duty cycle and frequency of PWM and is a special case of the
input capture mode. The operation is the same as input capture mode except for the following differences:
PWM occupies two compare capture channels and the input polarity of the two channels is set to opposite, one
of the signals is set as trigger input and SMS is set to reset mode.
For example, to measure the period and frequency of the PWM wave input from TI1, the following operations
are required.
1)
Set TI1 (TI1FP1) to be the input of IC1 signal. Set CC1S to 01b.
2)
Set TI1FP1 to rising edge active. Holding CC1P at 0.
3)
Set TI1 (TI1FP2) as the input of IC2 signal. Set CC2S to 10b.
4)
Select TI1FP2 to set to falling edge active. Set CC2P to 1.
5)
Select TI1FP1 as the source of the clock source. set TS to 101b.
6)
Set the SMS to reset mode, i.e. 100b.
7)
Enables input capture. cc1e and cc2e are set.
Thus the value of compare capture register 1 is the period of the PWM, and the value of compare capture
register 2 is its duty cycle.
10.3.5 PWM output mode
PWM output mode is one of the basic functions of the timer. PWM output mode is most commonly used to
determine the PWM frequency using the reload value and the duty cycle using the capture comparison register.
Set 110b or 111b in the OCxM field to use PWM mode 1 or mode 2, set the OCxPE bit to enable the preload
register, and finally set the ARPE bit to enable automatic reload of the preload register. Since the value of the
preload register can only be sent to the shadow register when an update event occurs, the UG bit needs to be
set to initialize all registers before the core counter starts counting. In PWM mode, the core counter and the
compare capture register are always comparing, and depending on the CMS bit, the timer is able to output
edge-aligned or center-aligned PWM signals.
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Edge alignment
When edge alignment is used, the core counter is incremented or decremented, and in the PWM mode 1
scenario, OCxREF is high when the core counter value is greater than the compare capture register, and low
when the core counter value is less than the compare capture register (e.g., when the core counter grows to the
value of R16_TIMx_ATRLR and reverts to all zeros).
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Central alignment
When using the central alignment modes, the core counter runs in alternating incremental and decremental
count modes, and OCxREF makes rising and falling jumps when the values of the core counter and the
compare capture register match. However, the comparison flags are set at different times in the three central
alignment modes. When using the central alignment modes, it is best to generate a software update flag (set
the UG bit) before starting the core counter.
10.3.6 Complementary outputs and dead zones
The comparison capture channel generally has two output pins (comparison capture channel 4 has only one
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