Spi Mode - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
determined by SSI, this case is generally used in SPI Master mode.
2) NSS is controlled by hardware: when NSS output is enabled, i.e., when SSOE is set, the NSS pin will be
actively pulled low when the SPI host sends output outward, and a hardware error will be generated if the
NSS pin is pulled low; if SSOE is not set, it can be used in Multi-master mode, and if it is pulled low it
will be forced into Slave mode and the MSTR bit will be cleared automatically.
CPHA is set to indicate that the module samples data on the second edge of the clock and the data is latched,
while CPHA is not set to indicate that the SPI module samples data on the first edge of the clock and the data
is latched, and CPOL indicates whether the clock is held high or low when there is no data. See Figure 14-2
below for details.
The host and device need to be set to the same SPI mode, and the SPE bit needs to be cleared before configuring
the SPI mode. the DEF bit determines whether the individual data length of the SP is 8 bits or 16 bits.
14.2.2 Master mode
The serial clock is generated by SCK when the SPI module is operating in master mode. The following steps
are performed to configure into master mode.
The BR[2:0] field of the configuration control register to determine the clock.
Configure the CPOL and CPHA bits to determine the SPI mode.
Configuring DEF to determine the data word length.
V1.3
Figure 14-2 SPI Mode
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