Serial Peripheral Interface (Spi); Spi Structure Block Diagram - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Chapter 14 Serial Peripheral Interface (SPI)
SPI supports data interaction in a three-wire synchronous serial mode, plus a chip selector line to support
hardware switching between Master and Slave modes, and supports communication on a single data line.
14.1 Main features
l Support full-duplex synchronous serial mode
l Support single-line half-duplex mode
l Support Master mode and Slave mode, Multi-slave mode
l Support 8-bit or 16-bit data structures
l Maximum clock frequency supports up to half of Fpclk
l Data order only supports MSB first
l Support hardware or software control of NSS pins
l Hardware CRC checksum support for sending and receiving
l Transceiver buffers support DMA transfers
l
Support modification of clock phase and polarity
14.2 Function Description
14.2.1 Overview
MOSI
MISO
SCK
NSS
As can be seen from Figure 14-1, the four main SPI-related pins are MISO, M0SI, SCK and NSS. The MISO
pin is the data input pin when the SPI module is operating in Master mode and the data output pin when it is
operating in Slave mode. the MOSI pin is the data output pin when it is operating in Master mode and the data
input pin when it is operating in Slave mode. the SCK is the clock pin, the clock signal is always output by the
host and the slave receives the clock signal and synchronizes the data sending and receiving. the NSS pin is
the chip select pin with the following usage.
1) NSS controlled by software: when SSM is set and the internal NSS signal is output high or low as
V1.3
Figure 14-1 SPI structure block diagram
Address and data bus
Read
Rx buffer
Shift register
LSB first
Tx buffer
Write
Baud rate generator
Master control logic
157
SPI_CTLR2
TXE RXNE ERR
0 0
IE IE IE
SPI_CTATR
OVR MOD CRC
BSY 0
F ERR
Communication
control
BR[2:0]
LSB
SPE BR2 BR1 BR0 MSTR CPOL CPHA
FIRST
SPI_CTLR1
BIDI BIDI CRC CRC
Next DFF
MODE OE EN
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SSOE TXDM RXDM
AEN AEN
0 TXE RXNE
0
1
RX
ONLY SSM SSI