Adc Watchdog High Threshold Register (Adc_Wdhtr); Adc Watchdog Low Threshold Register (Adc_Wdhtr); Adc Regular Sequence Register 1(Adc_Rsqr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Bit Name
[31:10] Reserved
[9:0] JOFFSETx

9.3.7 ADC Watchdog high threshold register (ADC_WDHTR)

Offset address: 0x24
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
[9:0] HT
Note: You can change the values of WDHTR and WDLTR during the conversion process, but they will take
effect at the next conversion.

9.3.8 ADC Watchdog low threshold register (ADC_WDHTR)

Offset address: 0x28
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
[9:0] LT
Note: You can change the values of WDHTR and WDLTR during the conversion process, but they will take
effect at the next conversion.

9.3.9 ADC Regular sequence register 1(ADC_RSQR1)

Offset address: 0x2C
31 30 29 28
Reserved
15 14 13 12
SQ16[0] SQ15[4:0]
V1.3
Access
RO Reserved
The data offset value of the injected channel x.
When converting the injected channels, this value defines
RW the value used to subtract from the original conversion
data. The result of the conversion can be read out in the
ADC_IDATARx register.
27 26 25 24
Reserved
11 10 9 8
Access
RO Reserved
RW Analog watchdog high threshold setting value.
27 26 25 24
Reserved
11 10 9 8
Access
RO Reserved
RW Analog watchdog low threshold setting value.
27 26 25 24
11 10 9 8
SQ14[4:0]
Description
23 22 21
7 6 5
HT[9:0]
Description
23 22 21
7 6 5
LT[9:0]
Description
23 22 21
L[3:0]
7 6 5
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Reset
value
20 19 18 17
4 3 2 1
Reset
value
20 19 18 17
4 3 2 1
Reset
value
20 19 18 17
RSQ16[4:1]
4 3 2 1
SQ13[4:0]
0
0
16
0
0
0
16
0
0
0
16
0