Pfic Interrupt Enable Clear Register 1 (Pfic_Irer1); Pfic Interrupt Enable Clear Register 2 (Pfic_Irer2); Pfic Interrupt Pending Setup Register 1 (Pfic_Ipsr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
15 14 13 12
Bit Name
[31:7] Reserved
[6:0] INTEN32_38

6.5.2.13 PFIC interrupt enable clear register 1 (PFIC_IRER1)

Offset address: 0x180
31 30 29 28
15 14 13 12
Reser INTRSE Rese INTRSET
ved T14 rved 12
Bit Name
[31:16] INTRSET16_31
15 Reserved
14 INTRSET14
13 Reserved
12 INTRSET12
[11:0] Reserved

6.5.2.14 PFIC interrupt enable clear register 2 (PFIC_IRER2)

Offset address: 0x184
31 30 29 28
15 14 13 12
Bit Name
[31:7] Reserved
[6:0] INTRSET32_38

6.5.2.15 PFIC interrupt pending setup register 1 (PFIC_IPSR1)

Offset address: 0x200
31 30 29 28
15 14 13 12
V1.3
11 10 9
Reserved
Access
RO Reserved
32#-38# interrupt enable control.
WO 1: current number interrupt enable.
0: No effect.
27 26 25
INTRESET[31:16]
11 10 9
Access
16#-31# interrupt shutdown control.
WO 1: current number interrupt off.
0: No effect.
RO Reserved
14# Interrupt off control.
WO 1: current number interrupt off.
0: No effect.
RO Reserved
12# Interrupt off control.
WO 1: current number interrupt off.
0: No effect.
RO Reserved
27 26 25
11 10 9
Reserved
Access
RO Reserved
32#-38# interrupt shutdown control.
WO 1: current number interrupt off.
0: No effect.
27 26 25
PENDSET[31:16]
11 10 9
8 7 6 5
Description
24 23 22 21
8 7 6 5
Reserved
Description
24 23 22 21
Reserved
8 7 6 5
Description
24 23 22 21
8 7 6 5
42
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4 3 2 1
INTEN[38:32]
Reset value
0
0
20 19 18 17
4 3 2 1
Reset value
0
0
0
0
0
0
20 19 18 17
4 3 2 1
INTRSET[38:32]
Reset value
0
0
20 19 18 17
4 3 2 1
0
16
0
16
0
16
0