WCH CH32V003 Series Reference Manual page 151

CH32V003 Reference Manual
10 ACK
9 STOP
8 START
7 NOSTRETCH
6 ENGC
5 ENPEC
[4:1] Reserved
0 PE
V1.3
hardware after the PE has been cleared.
1: ACK bit controls the ACK or NAK of the next
byte received in the shift register. The next byte
received in the PEC shift register is the PEC.
0: The ACK bit controls the ACK or NAK of the
byte currently being accepted in the shift register.
the PEC bit indicates that the byte in the shift
register before the current bit is PEC.
Note: The POS bit is used in 2-byte data reception
as follows: it must be configured before reception.
In order to NACK the 2nd byte, the ACK bit must
be cleared immediately after clearing the ADDR
bit; in order to detect the PEC of the second byte,
the PEC bit must be set after the ADDR event and
after configuring the POS bit.
Acknowledge enable, This bit is set and cleared
by software and cleared by hardware when PE=0.
RW
1：Acknowledge returned after a byte is received.
0：No acknowledge returned.
Stop generation bit. This bit is set and cleared by
software, cleared by hardware when a Stop
condition is detected, set by hardware when a
timeout error is detected.
In Master mode:
1：Stop generation after the current byte transfer
RW
or after the current Start condition is sent.
0：No Stop generation.
In Slave mode:
1：Release the SCL and SDA lines after the
current byte transfer.
0：No Stop generation.
Start generation. This bit is set and cleared by
software and cleared by hardware when start is
sent or PE=0.
In Master mode:
1：Repeated start generation
RW
0：No Start generation
In Slave mode:
1：Start generation when the bus is free
0：No Start generation
Clock stretching disable bit. This bit is used to
disable clock stretching in slave mode when
ADDR or BTF flag is set, until it is reset by
RW
software.
1：Clock stretching disabled.
0：Clock stretching enabled.
General call enable bit. Set this bit to enable
RW
broadcast call and answer broadcast address 00h.
PEC enable bit, set this bit to enable PEC
RW
calculation.
RO Reserved
I2C peripheral enable bit.
RW 1: Enable the I2C module.
0: Disable the I2C module.
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