Debug Support (Dbg); Debug Mcu Configuration Register (Dbgmcu_Cr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
18.1 Main features
This register allows the MCU to be configured in the debug state. It includes:
l Independent Watchdog (IWDG) enabled counters
l Window Watchdog (WWDG) enabled counters
l Timer1 enabled counters
l Timer2 enabled counters
18.2 Register description

18.2.1 Debug MCU Configuration Register (DBGMCU_CR)

Offset address: 0x7C0 (CSR)
31 30 29 28
15 14 13 12
Bit Name
[31:6] Reserved
5 TIM2_STOP
4 TIM1_STOP
[3:2] Reserved
1 WWDG_STOP
0 IWDG_STOP
V1.3
Chapter 18 Debug Support (DBG)
27 26 25 24
Reserved
11 10 9 8
Reserved
Access
RW Reserved
Timer 2 debug stop bit. The counter stops when
the core enters the debug state.
RW
1: Timer 2's counter stops working.
0: Timer 2's counter is still working normally.
Timer 1 debug stop bit. The counter stops when
the kernel enters the debug state.
RW
1: Timer 1's counter stops working.
0: Timer 1's counter is still working normally.
RW Reserved
WWDG debug stop bit. The debug WWDG stops
working when the core enters the debug state.
RW
1: WWDG counter stops working.
0: WWDG counter is still working normally.
IWDG debug stop bit. The debug IWDG stops
working when the core enters the debug state.
RW
1: IWDG counter stops working.
0: IWDG counter is still working normally.
23 22 21
7 6 5
TIM2 TIM1
_STO _STO
P
Description
181
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20 19 18 17
4 3 2 1
WW
Reserved DG_S
P TOP
Reset value
0
0
0
0
0
0
16
0
IWD
G_ST
OP