Control Register (Iwdg_Ctlr); Debug Mode; Prescaler Register - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
a system reset from occurring. Write 0xAAAA to the IWDG_CTLR register to allow the hardware to
update the IWDG_RLDR register value to the watchdog counter. This action needs to be executed
regularly after the watchdog function is turned on, otherwise a watchdog reset action will occur.

4.2.2 Debug mode

When the system enters Debug mode, the counter of IWDG can be configured by the debug module register
to continue or stop.
4.3 Register description
Name
R16_IWDG_CTLR
R16_IWDG_PSCR
R16_IWDG_RLDR
R16_IWDG_STATR

4.3.1 Control register (IWDG_CTLR)

Offset address: 0x00
15 14 13 12
Bit Name
[15:0] KEY
4.3.2 Prescaler register (IWDG_PSCR)
Offset address: 0x04
15 14 13 12
Bit Name
[15:3] Reserved
[2:0] PR
V1.3
Table 4-1 IWDG-related registers list
Access address
0x40003000 Control register
0x40003004

Prescaler register

0x40003008 Reload register
0x4000300C Status register
11 10 9 8
KEY[15:0]
Access
Operate the key value lock.
00xAAAA: Feed the dog. Loading of the
IWDG_RLDR register value into the independent
watchdog counter.
0x5555:
WO
R16_IWDG_PSCR and R16_IWDG_ RLDR
registers.
0xCCCC: Start the watchdog, but not if the
hardware watchdog is enabled (user-selected word
configuration).
11 10 9 8
Reserved
Access
RO Reserved
IWDG clock division factor, write 0x5555 to KEY
before modifying this field.
000: Divided by 4; 001: Divided by 8.
010: Divided by 16; 011: Divided by 32.
100: Divided by 64; 101: Divided by 128.
RW
110: Divided by 256; 111: Divided by 256.
IWDG counting time base = LSI/divide factor.
Note: Before reading the value of this field, make
sure the PVU bit in the IWDG_STATR register is
0, otherwise the read value is invalid.
Description
7 6 5
Description
Allows modification
7 6 5
Description
26
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Reset value
0x0000
0x0000
0x0FFF
0x0000
4 3 2 1
Reset value
of the
0
4 3 2 1
PR[2:0]
Reset value
0
0
0
0