Adc-Related Registers List; Adc Status Register (Adc_Statr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
9.3 Register description
Name
R32_ADC_STATR
R32_ADC_CTLR1
R32_ADC_CTLR2
R32_ADC_SAMPTR1
R32_ADC_SAMPTR2
R32_ADC_IOFR1
R32_ADC_IOFR2
R32_ADC_IOFR3
R32_ADC_IOFR4
R32_ADC_WDHTR
R32_ADC_WDLTR
R32_ADC_RSQR1
R32_ADC_RSQR2
R32_ADC_RSQR3
R32_ADC_ISQR
R32_ADC_IDATAR1
R32_ADC_IDATAR2
R32_ADC_IDATAR3
R32_ADC_IDATAR4
R32_ADC_RDATAR
R32_ADC_DLYR

9.3.1 ADC Status register (ADC_STATR)

Offset address: 0x00
31 30 29 28
15 14 13 12
Bit Name
[31:5] Reserved
4 STRT
3 JSTRT
2 JEOC
1 EOC
V1.3
Table 9-5 ADC-related registers list
Access address
0x40012400 ADC status register
0x40012404 ADC control register 1
0x40012408 ADC control register 2
0x4001240C ADC sample time register 1
0x40012410 ADC sample time register 2
0x40012414 ADC injected channel data offset register 1
0x40012418 ADC injected channel data offset register 2
0x4001241C ADC injected channel data offset register 3
0x40012420 ADC injected channel data offset register 4
0x40012424 ADC watchdog high threshold register
0x40012428 ADC watchdog low threshold register
0x4001242C ADC regular sequence register 1
0x40012430 ADC regular sequence register 2
0x40012434 ADC regular sequence register 3
0x40012438 ADC injected sequence register
0x4001243C ADC injected data register 1
0x40012440 ADC injected data register 2
0x40012444 ADC injected data register 3
0x40012448 ADC injected data register 4
0x4001244C ADC regular data register
0x40012450 ADC delayed data register
27 26 25 24
Reserved
11 10 9 8
Reserved
Access
RO Reserved
Rule channel transition start state.
1: Rule channel conversion has begun.
RW0 0: Rule channel conversion is not started.
This bit is set to 1 by hardware and cleared to 0 by software
(write 1 is not valid).
Injection channel conversion start state.
1: Injection channel conversion has started.
RW0 0: Injection channel conversion has not started.
This bit is set to 1 by hardware and cleared to 0 by software
(write 1 is not valid).
Injection into the end state of the channel group
conversion.
1: Conversion complete.
RW0
0: The conversion is not completed.
This bit is set to 1 by hardware (all injected channels are
converted) and cleared to 0 by software (write 1 is invalid).
RW0 Conversion end state.
Description
23 22 21
7 6 5
STRT
Description
77
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Reset value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
20 19 18 17
4 3 2 1
JSTR
JEOC EOC AWD
T
Reset
value
16
0
0
0
0
0
0