Channel Configuration; Calibration; Programmable Sampling Time; Data Alignment - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
3)

Channel configuration

The ADC module provides 10 channel sampling sources, including 8 external channels and 2 internal channels.
They can be configured into two types of conversion groups: regular groups and injection groups. to achieve
a group conversion consisting of a series of conversions in any order on any number of channels.
Conversion group.
l Rule group: consists of up to 16 conversions. The rule channels and their conversion order are set in the
ADC_RSQRx register. The total number of conversions in the rule group should be written to RLEN[3:0]
in the ADC_RSQR1 register.
l Injection group: consists of up to 4 conversions. The injection channels and the order of their conversions
are set in the ADC_ISQR register. The total number of conversions in the injection group should be
written in ILEN[1:0] of the ADC_ISQR register.
Note: If the ADC_RSQRx or ADC_ISQR registers are changed during conversion, the current conversion is
terminated and a new start signal is sent to the ADC to convert the newly selected group.
2 internal channels.
l Vref internal reference voltage: connected to ADC_IN8 channel.
l Vcal internal calibration voltage: connected to ADC_IN9 channel, 2 steps selectable.
4)

Calibration

The ADC has a built-in self-calibration mode. A calibration session significantly reduces accuracy errors due
to variations in the internal capacitor banks. During calibration, an error correction code is calculated on each
capacitor, which is used to eliminate the errors generated on each capacitor in subsequent conversions.
Initialize the calibration register by writing RSTCAL position 1 of ADC_CTLR2 register and wait for
RSTCAL hardware to clear 0 to indicate the completion of initialization. Set the CAL bit to start the calibration
function. Once the calibration is finished, the hardware will automatically clear the CAL bit and store the
calibration code into ADC_RDATAR. After that, the normal conversion function can be started. It is
recommended to perform an ADC calibration when the ADC module is powered up.
Note: Before starting the calibration, you must ensure that the ADC module is in the power-up state (ADON=1)
for more than at least two ADC clock cycles.
5)

Programmable sampling time

The ADC uses several ADCCLK cycles to sample the input voltage. The number of sampling cycles for a
channel can be changed using the SMPx[2:0] bits in the ADC_SAMPTR1 and ADC_SAMPTR2 registers.
Each channel can be sampled separately using a different time.
The total conversion time is calculated as follows.
The ADC's rule channel conversion supports the DMA function. The value of the rule channel conversion is
stored in a data-only register, ADC_RDATAR. To prevent the data in ADC_RDATAR register from being
fetched in time when multiple rule channels are converted in succession, the DMA function of ADC can be
enabled. The hardware will generate a DMA request at the end of the conversion of a rule channel (EOC set)
and transfer the converted data from the ADC_RDATAR register to the user-specified destination address.
After the channel configuration of the DMA controller module is completed, write DMA position 1 of the
ADC_CTLR2 register to enable the DMA function of the ADC.
Note: Injection group conversion does not support DMA function.
6)

Data alignment

The ALIGN bit in the ADC_CTLR2 register selects the alignment of the ADC converted data storage. 12-bit
data supports left-aligned and right-aligned modes.
The data register ADC_RDATAR of the rule group channel holds the actual converted 12-bit digital value;
while the data register ADC_IDATARx of the injection group channel is the actual converted data minus the
V1.3
T = sampling time + 11T
CONV
72
ADCCLK
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