Simplex Mode; Crc - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual http://wch.cn
Configure the NSS pin, for example by setting the SSOE bit and letting the hardware set the NSS. it is also
possible to set the SSM bit and set the SSI bit high.
To set the MSTR bit and the SPE bit, you need to make sure that the NSS is already high at this time.
When data needs to be sent just write the data to be sent to the data register. SPI will send the data from the
send buffer to the shift register in parallel, when the data has reached the shift register, the TXE flag will be
set, if the TXEIE has been set, then an interrupt will be generated. If the TXE flag position bit needs to fill the
data register with data to maintain the complete data flow.
When the receiver receives data, when the last sample clock edge of the data word comes, the data is transferred
from the shift register to the receive buffer in parallel, the RXNE bit is set, and an interrupt is generated if the
RXNEIE bit was previously set. At this time, the data register should be read as soon as possible to take away
the data.
14.2.3 Slave mode
When the SPI module is operating in slave mode, SCK is used to receive the clock from the host and its own
baud rate setting is invalid. To configure into slave mode, proceed as follows.
Configuring the DEF bit to set the data bit length.
Configure the CPOL and CPHA bits to match the host mode. the NSS pin needs to be held low in hardware
management mode, if NSS is set to software management (SSM set), then keep SSI unset.
Clear the MSTR bit and set the SPE bit to enable SPI mode. In transmitting, when the first slave receive sample
edge appears in SCK, the slave starts to transmit. The process of sending is to move the data in the transmit
buffer t the transmit shift register. When the data in the transmit buffer is moved to the shift register, the TXE
flag will be set, and if the TXEIE bit was set before, then an interrupt will be generated.
During reception, after the last clock sample edge, the RXNE bit is set, the bytes received by the shift register
are transferred to the receive buffer, and the read operation of the read data register can obtain the data in the
receive buffer. If RXNEIE is set before RXNE is set, then an interrupt is generated.

14.2.4 Simplex mode

The SPI interface can operate in half-duplex mode, where the master device uses the MOSI pin and the slave
device uses the MISO pin for communication. When using half-duplex communication, you need to set
BIDIMODE and use BIDIOE to control the transmission direction.
Setting the RXONLY bit in normal full-duplex mode sets the SPI module to receive-only simplex mode,
releasing a data pin after RXONLY is set. The SPI can also be set to transmit only mode by ignoring the
received data.

14.2.5 CRC

The SPI module uses CRC checksum to ensure the reliability of full-duplex communication, and separate CRC
calculators are used for data sending and receiving. the polynomial for CRC calculation is determined by the
polynomial register, and different calculations are used for 8-bit data width and 16-bit data width, respectively.
Setting the CRCEN bit will enable CRC checksum and at the same time will reset the CRC calculator. After
the last data byte is sent, setting the CRCNEXT bit will send the TXCRCR calculator calculation after the
current byte is sent, while the CRCERR bit will be set if the last received receive shift register value does not
match the locally calculated RXCRCR calculation. Using the CRC checksum requires setting the polynomial
calculator and setting the CRCEN bit when configuring the SPI operating mode, and setting the CRCNEXT
bit on the last word or half-word to send the CRC and perform the receive CRC checksum. Note that the
polynomial for the CRC calculation should be unified for both sending and receiving.
14.2.6 DMA
The SPI module supports the use of DMA to speed up data communication, either by using DMA to fill the
transmit buffer or by using DMA to pick up data from the receive buffer in a timely manner. DMA will pick
up or send data in a timely manner using RXNE and TXE as signals. DMA can also operate in simplex or CRC
mode.
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