User-Selected Word Unlocking; User-Selected Word Programming - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
STANDBY
2
_RST
1 Reserved
0 IWDG_SW
Data0–Data1
WRPR0 - WRPR3

16.5.1 User-selected word unlocking

The user select word operation can be unlocked by writing a sequence to the FLASH_OBKEYR register. After
unlocking, the OBWRE bit of FLASH_CTLR register will be set to 1, indicating that the user select word can
be erased and programmed. It can be locked again by clearing the "OBWRE" bit of FLASH_CTLR register to
0 by software.
Unlock sequence.
1) Write KEY1 = 0x45670123 to FLASH_OBKEYR register.
2) Write KEY2 = 0xCDEF89AB to FLASH_OBKEYR register.
Note: User-selected word operation requires unlocking the "LOCK" and "OBWRE" layers.

16.5.2 User-selected word programming

Only the standard programming method is supported, writing half-words (2 bytes) at a time. In practice, when
programming the user-selected word, FPEC uses only the low byte in the half-word and automatically
calculates the high byte (the high byte is the inverse of the low byte) and then starts the programming operation,
which will ensure that the byte in the user-selected word and its inverse code are always correct.
1) Check the LOCK bit of FLASH_CTLR register, if it is 1, you need to execute the "Unlock Flash"
operation.
2) Check the BSY bit of the FLASH_STATR register to confirm that there are no other programming
operations in progress.
3) Set the OBPG bit of FLASH_CTLR register to '1', after that set the STAT bit of FLASH_CTLR register
to '1' to turn on the user select word programming.
4) Set the OBPG bit of FLASH_CTLR register to '1', after that set the STAT bit of FLASH_CTLR register
to '1' to turn on the user select word programming.
5) Write the half word (2 bytes) to be programmed to the specified address.
6) Wait for the BYS bit to become '0' or the EOP bit of FLASH_STATR register to be '1' to indicate the end
V1.3
Low-power management reset configuration for standby
mode.
1: Enabling low-power management reset for Standby
mode.
0: Disable low-power management reset for Standby
mode.
Reserved
Independent Watchdog (IWDG) hardware enable
configuration.
1: IWDG is enabled by software and disabled from being
enabled by hardware.
0: IWDG is turned on by hardware itself (since the clock
for IWDG is provided by LSI, it is automatically turned
on by LSI).
Note: The core stops in debug mode and the watchdog
hardware enable will be disabled.
Store 2 bytes of user data.
Write-protect control bits. Each bit is used to control the
write-protect status of 1 sector (1K bytes/sector) in main
memory.
1: Turn off write protection.
0: Write protection is enabled.
4 bytes are used to protect a total of 16K bytes of main
memory.
WRPO: sector 0-3 storage write protection control.
WRP1: sector 4-7 storage write protection control.
WRP2: Sector 8-11 storage write protection control.
WRP3: Write protection for sectors 12-15.
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1
1
1
FFFFh
FFFFFFFFh