Adc Regular Sequence Register 2(Adc_Rsqr2); Adc Regular Sequence Register 3(Adc_Rsqr3) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Bit Name
[31:24] Reserved
[23:20] L
[19:15] SQ16
[14:10] SQ15
[9:5] SQ14
[4:0] SQ13

9.3.10 ADC Regular sequence register 2(ADC_RSQR2)

Offset address: 0x30
31 30 29 28
Reserved
15 14 13 12
SQ10[0] SQ9[4:0]
Bit Name
[31:30] Reserved
[29:25] SQ12
[24:20] SQ11
[19:15] SQ10
[14:10] SQ9
[9:5] SQ8
[4:0] SQ7

9.3.11 ADC Regular sequence register 3(ADC_RSQR3)

Offset address: 0x34
31 30 29 28
Reserved
15 14 13 12
SQ4[0] SQ3[4:0]
Bit Name
[31:30] Reserved
[29:25] SQ6
[24:20] SQ5
V1.3
Access
RO Reserved
Number of channels to be converted in a regular channel
RW conversion sequence.
0000-1111: 1-16 conversions.
The number of the 16th conversion channel in the rule
RW
sequence (0-9).
The number of the 15th conversion channel in the rule
RW
sequence (0-9).
The number of the 14th conversion channel in the rule
RW
sequence (0-9).
The number of the 13th conversion channel in the rule
RW
sequence (0-9).
27 26 25
SQ12[4:0]
11 10 9
Access
RO Reserved
The number of the 12th conversion channel in the rule
RW
sequence (0-9).
The number of the 11th conversion channel in the rule
RW
sequence (0-9).
The number of the 10th conversion channel in the rule
RW
sequence (0-9).
The number of the 9th conversion channel in the rule
RW
sequence (0-9).
The number of the 8th conversion channel in the rule
RW
sequence (0-9).
The number of the 7th conversion channel in the rule
RW
sequence (0-9).
27 26 25
SQ6[4:0]
11 10 9
Access
RO Reserved
The number of the 6th conversion channel in the rule
RW
sequence (0-9).
The number of the 5th conversion channel in the rule
RW
sequence (0-9).
Description
24 23 22 21
SQ11[4:0]
8 7 6 5
SQ8[4:0]
Description
24 23 22 21
SQ5[4:0]
8 7 6 5
SQ2[4:0]
Description
83
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Reset
value
20 19 18 17
SQ10[4:1]
4 3 2 1
SQ7[4:0]
Reset
value
20 19 18 17
SQ4[4:1]
4 3 2 1
SQ1[4:0]
Reset
value
0
0
0
0
0
0
16
0
0
0
0
0
0
0
0
16
0
0
0
0