Independent Watchdog (Iwdg); Enable Independent Watchdog; Watchdog Configuration - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Chapter 4 Independent Watchdog (IWDG)
The system is equipped with an independent watchdog (IWDG) to detect logic errors and software faults
caused by external environmental disturbances. the IWDG clock source is derived from the LSI and can run
independently of the main program, making it suitable for applications requiring low accuracy.
4.1 Main features
l 12-bit self-subtracting counter
l Clock source LSI divider, can run in low-power mode
l Reset condition: Counter value is reduced to 0
4.2 Function description
4.2.1 Principle and application
The independent watchdog is clocked from the LSI clock divider and its function remains functional during
shutdown and Standby modes. When the watchdog counter self-decreases to 0, a system Reset will be
generated, so the timeout is (reload value + 1) clock.
Figure 4-1 Block diagram of the structure of the independent watchdog
CORE
Prescaler register
IWDG_PR
8-bit
LSI
prescaler
(128kHz)
VDD voltage domain
l

Enable independent watchdog

After a system reset, the watchdog is off and writing 0xCCCC to the IWDG_CTLR register turns the watchdog
on, after which it cannot be turned off again unless a reset occurs.
If the hardware independent watchdog enable bit (IWDG_SW) is turned on at the user-selected word, IWDG
will be fixed on after a microcontroller reset.
l

Watchdog configuration

The watchdog is internally a 12-bit counter that runs decreasingly. When the counter value decreases to 0, a
system Reset will occur. To turn on the IWDG function, the following actions need to be performed.
1) Counting time base: IWDG clock source LSI, set the LSI crossover value clock as the counting time base
of IWDG through the IWDG_PSCR register. The operation method first writes 0x5555 to the
IWDG_CTLR register, and then modifies the crossover value in the IWDG_PSCR register. the PVU bit
in the IWDG_STATR register indicates the update status of the crossover value, and the crossover value
can be modified and read out only when the update is completed.
2) Reload value: Used to update the current value of the counter in the standalone watchdog and the counter
is decremented by this value. The RVU bit in the IWDG_STATR register indicates the update status of
the reload value, and the IWDG_RLDR register can be modified and read out only when the update is
completed.
3) Watchdog enable: write 0xCCCC to the IWDG_CTLR register to enable the watchdog function.
4) Feed the dog: i.e., flush the current counter value before the watchdog counter decrements to 0 to prevent
V1.3
Status register Reload register
IWDG_SR IWDG_RLR
12-bit reload value
12-bit downcounter
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Key register
IWDG_KR
IWDG reset