Pfic Vtf Interrupt 1 Address Register (Pfic_Vtfaddrr1); Pfic Interrupt Enable Setting Register 1 (Pfic_Ienr1); Pfic Interrupt Enable Setting Register 2 (Pfic_Ienr2) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Bit Name
[31:1] ADDR0
0 VTF0EN

6.5.2.10 PFIC VTF interrupt 1 address register (PFIC_VTFADDRR1)

Offset address: 0x64
31 30 29 28
15 14 13 12
Bit Name
[31:1] ADDR1
0 VTF1EN

6.5.2.11 PFIC interrupt enable setting register 1 (PFIC_IENR1)

Offset address: 0x100
31 30 29 28
15 14 13 12
Reser INTEN1 Rese
INTEN12
ved 4 rved
Bit Name
[31:16] INTEN16_31
15 Reserved
14 INTEN14
13 Reserved
12 INTEN12
[11:0] Reserved

6.5.2.12 PFIC interrupt enable setting register 2 (PFIC_IENR2)

Offset address: 0x104
31 30 29 28
V1.3
Access
VTF interrupt 0 service program address
RW
bit[31:1], bit0 is 0.
VTF interrupt 0 enable bit.
RW 1: enable VTF interrupt 0 channel;
0: off.
27 26 25 24
ADDR1[31:16]
11 10 9 8
ADDR1[15:1]
Access
VTF interrupt 1 service program address
RW
bit[31:1], bit0 is 0.
VTF interrupt 1 enable bit.
RW 1: VTF interrupt 1 channel is enabled;
0: Off.
27 26 25 24
INTEN[31:16]
11 10 9 8
Access
16#-31# interrupt enable control.
WO 1: current number interrupt enable.
0: No effect.
RO Reserved
14# Interrupt enable control.
WO 1: current number interrupt enable.
0: No effect.
RO Reserved
12# Interrupt enable control.
WO 1: current number interrupt enable.
0: No effect.
RO Reserved
27 26 25 24
Reserved
Description
23 22 21
7 6 5
Description
23 22 21
7 6 5
Reserved
Description
23 22 21
41
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Reset value
0
0
20 19 18 17
4 3 2 1
Reset value
0
0
20 19 18 17
4 3 2 1
Reset value
0
0
0
0
0
0
20 19 18 17
16
0
VTF1E
N
16
0
16