Dma Request Mapping - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
function with programmable pointer increments. The first transmitted data address they access is stored in the
DMA_PADDRx and DMA_MADDRx registers.By setting the PINC bit or MINC position 1 of the
DMA_CFGRx register, the peripheral address self-increment mode or memory address self-increment mode
can be enabled, respectively. PSIZE[1:0] sets the peripheral address fetch data size and address selfincrement
size. MSIZE[1:0] sets the memory address to take the data size and address self-increasing small, including
three choices: 8-bit, 16-bit, 32-bit. The specific data transfer methods are listed in the following table.
Table 8-1 DMA transfer with different data bit widths (PINC=MINC=1)
Source
Objectives Transmission
bit
bit width number
width
8 8
8 16
8 32
16 8
16 16
16 32
32 8
32 16
32 32

8.2.3 DMA request mapping

The DMA controller provides seven channels, each corresponding to multiple peripheral requests. By setting
the corresponding DMA control bits in the corresponding peripheral registers, the DMA function of each
peripheral can be turned on or off independently, and the specific correspondence is as follows.
V1.3
Source:
address/data
0x00/B0
0x01/B1
4
0x02/B2
0x03/B3
0x00/B0
0x01/B1
4
0x02/B2
0x03/B3
0x00/B0
0x01/B1
4
0x02/B2
0x03/B3
0x00/B1B0
0x02/B3B2
4
0x04/B5B4
0x06/B7B6
0x00/B1B0
0x02/B3B2
4
0x04/B5B4
0x06/B7B6
0x00/B1B0
0x02/B3B2
4
0x04/B5B4
0x06/B7B6
0x00/B3B2B1B0
0x04/B7B6B5B4
4
0x08/BBBAB9B8
0x0C/BFBEBDBC
0x00/B3B2B1B0
0x04/B7B6B5B4
4
0x08/BBBAB9B8
0x0C/BFBEBDBC
0x00/B3B2B1B0
0x04/B7B6B5B4
4
0x08/BBBAB9B8
0x0C/BFBEBDBC
Target: address/data
0x00/B0
0x01/B1
0x02/B2
0x03/B3
0x00/00B0
0x02/00B1
0x04/00B2
0x06/00B3
0x00/000000B0
0x04/000000B1
0x08/000000B2
0x0C/000000B3
0x00/B0
0x01/B2
0x02/B4
0x03/B6
0x00/B1B0
0x02/B3B2
0x04/B5B4
0x06/B7B6
0x00/0000B1B0
0x04/0000B3B2
0x08/0000B5B4
0x0C/0000B7B6
0x00/B0
0x01/B4
0x02/B8
0x03/BC
0x00/B1B0
0x02/B5B4
0x04/B9B8
0x06/BDBC
0x00/B3B2B1B0
0x04/B7B6B5B4
0x08/BBBAB9B8
0x0C/BFBEBDBC
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Transfer operations
l The source address
increment is aligned with
the data bit width set at
the source and takes a
value equal to the data bit
width at the source
l The target address
increment is aligned with
the bit width of the target
setup data and takes a
value equal to the target
data bit width
l DMA transfer of data
sent to the target based on
the principle: the high bit
of the data size is not
enough to make up 0, the
high bit of the data size
overflow is removed
l Storage data
small-end mode,
address stores low bytes,
high address stores high
bytes
mode:
low