Event Generation Register (Tim1_Swevgr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
8 Reserved
7 BIF
6 TIF
5 COMIF
4 CC4IF
3 CC3IF
2 CC2IF
1 CC1IF
0 UIF

10.4.6 Event generation register (TIM1_SWEVGR)

Offset address: 0x14
15 14 13 12
V1.3
1: the value of the counter is captured into the capture
comparison register when the status of CC1IF has been
set.
0: No duplicate captures are generated.
RO Reserved
The brake interrupt flag bit, once the brake input is
valid, by hardware for this position bit, can be cleared
RW0 by software.
1: A set valid level is detected on the brake pin input.
0: No braking event is generated.
Trigger interrupt flag bit, when a trigger event occurs
by hardware to this location bit, by software to clear.
Trigger events include the detection of a valid edge at
RW0 the TRGI input from a mode other than gated, or any
edge in gated mode.
1: Trigger event generation.
0: No trigger event is generated.
COM interrupt flag bit, this bit is set by hardware and
cleared by software once a COM event is generated.
com events including CCxE, CCxNE, OCxM are
RW0
updated.
1: COM event generation.
0: No COM event is generated.
RW0 Compare capture channel 4 interrupt flag bits.
RW0 Compare capture channel 3 interrupt flag bits.
RW0 Compare capture channel 2 interrupt flag bits.
Compare capture channel 1 interrupt flag bits.
If the compare capture channel is configured in output
mode.
This bit is set by hardware when the counter value
matches
centrosymmetric mode. This bit is cleared by software.
1: The value of the core counter matches the value of
compare capture register 1;
RW0
0: No match occurs.
If compare capture channel 1 is configured as input
mode. This bit is set by hardware when a capture event
occurs, and it is cleared by software or by reading the
compare capture register.
1: the counter value has been captured compare capture
register 1.
0: No input capture is generated.
Update interrupt flag bit, this bit is set by hardware
when an update event is generated and cleared by
software.
1: Update interrupt generation.
0: No update event is generated.
The following scenarios generate update events.
RW0
If UDIS = 0, when the repeat counter value overflows
or underflows.
If URS = 0, UDIS = 0, when the UG bit is set, or when
the counter core counter is reinitialized by software.
If URS = 0, UDIS = 0, when the counter CNT is
reinitialized by a trigger event.
11 10 9 8
the comparison
7 6 5
102
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value, except in
4 3 2 1
0
0
0
0
0
0
0
0
0
0