External Interrupt Configuration Register 1 (Afio_Exticr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[7:6] TIM1RM
[5:3] Reserved
2 USART1_RM
1 I2C1RM
0 SPI1RM

7.3.2.2 External interrupt configuration register 1 (AFIO_EXTICR)

Offset address: 0x08
31 30 29 28
15 14 13 12
V1.3
00: Default mapping (CH1/ETR/PD4, CH2/PD3,
CH3/PC0, CH4/PD7).
01: Partial mapping (CH1/ETR/PC5, CH2/PC2,
CH3/PD2, CH4/PC1).
10: Partial mapping (CH1/ETR/PC1, CH2/PD3,
CH3/PC0, CH4/PD7).
11: Complete
CH2/PC7, CH3/PD6, CH4/PD5).
Remap bits for timer 1. These bits can be read and
written by the user.
It controls the mapping of channels 1 to 4, 1N to
3N, external trigger (ETR) and brake input
(BKIN) of timer 1 to the GPIO ports.
00: Default mapping (ETR/PC5, CH1/PD2,
CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2,
CH1N/PD0, CH2N/PA2, CH3N/PD1).
RW 01: Partial mapping (ETR/PC5, CH1/PC6,
CH2/PC7, CH3/PC0, CH4/PD3, BKIN/PC1,
CH1N/PC3, CH2N/PC4, CH3N/PD1).
10: Partial mapping (ETR/PD4, CH1/PD2,
CH2/PA1, CH3/PC3, CH4/PC4, BKIN/PC2,
CH1N/PD0, CH2N/PA2, CH3N/PD1).
11: Complete mapping (ETR/PC2, CH1/PC4,
CH2/PC7, CH3/PC5, CH4/PD4, BKIN/PC1,
CH1N/PC3, CH2N/PD2, CH3N/PC6).
RO Reserved
USART1 mapping configuration low bit (used in
conjunction with AFIO PCFR1 register bit21
USART1REMAP1 [21,2]).
00: Default
RX/PD6, CTS/PD3, RTS/PC2, SW_RX/PD5).
RW 01: Remapping (CK/PD7, TX/PD0, RX/PD1,
CTS/PC3, RTS/PC2, SW_RX/PD0).
10: Remapping (CK/PD7, TX/PD6, RX/PD5,
CTS/PC6, RTS/PC7, SW_RX/PD6).
11: Remapping (CK/PC5, TX/PC0, RX/PC1,
CTS/PC6, RTS/PC7, SW_RX/PC0).
I2C1 remapping low bit (used in conjunction with
AFIO_PCFR1 register bit22 I2C1_RM1 [22,1]).
RW 00: Default mapping (SCL/PC2, SDA/PC1).
01: Remapping (SCL/ PD1, SDA/ PD0).
1X: Remapping (SCL/PC5, SDA/PC6)
Remapping of SPI1. This bit can be read or written
by the user. It controls the mapping of SPI1's NSS,
SCK, MISO, and MOSI multiplexing functions to
the GPIO ports.
RW
0: Default
MISO/PC7, MOSI/PC6).
1: Remapping (NSS/PC0, CK/PC5, MISO/PC7,
MOSI/PC6).
27 26 25 24
Reserved
11 10 9 8
mapping (CH1/ETR/PC1,
mapping (CK/PD4,
mapping (NSS/PC1,
23 22 21 20
7 6 5
60
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0
0
TX/PD5,
0
0
0
CK/PC5,
19 18 17
4 3 2 1
16
0