Adc Sample Time Configuration Register 1 (Adc_Samptr1); Adc Sample Time Configuration Register 2 (Adc_Samptr2); Adc Injected Channel Data Offset Register X (Adc_Iofrx) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

9.3.4 ADC Sample time configuration register 1 (ADC_SAMPTR1)

Offset address: 0x0C
31 30 29 28
15 14 13 12
SMP15[0
SMP14[2:0]
]
Bit Name
[31:18] Reserved
[17:0] SMPx

9.3.5 ADC Sample time configuration register 2 (ADC_SAMPTR2)

Offset address: 0x10
31 30 29 28
Reserved SMP9[2:0]
15 14 13 12
SMP5[0] SMP4[2:0]
Bit Name
[31:30] Reserved
[29:0] SMPx
9.3.6 ADC Injected channel data offset register x (ADC_IOFRx) (x=1/2/3/4)
Offset address: 0x14 + (x-1)*4
31 30 29 28
15 14 13 12
Reserved
V1.3
down mode.
Note: A conversion is initiated when only ADON is
changed in the register, and no new conversion is initiated
if there are any other bits sent for change.
27 26 25 24
Reserved
11 10 9 8
SMP13[2:0] SMP12[2:0]
Access
RO Reserved
SMPx[2:0]: sample time configuration for channel x.
000: 3 cycles; 001: 9 cycles.
010: 15 cycles; 011: 30 cycles.
100: 43 cycles; 101:57 cycles.
RW
110: 73 cycles; 111: 241 cycles.
These bits are used to independently select the sample time
for each channel, and the channel configuration value must
remain constant during the sample cycle.
27 26 25 24
SMP8[2:0]
11 10 9 8
SMP3[2:0] SMP2[2:0]
Access
RO Reserved
SMPx[2:0]: sample time configuration for channel x.
000: 3 cycles; 001: 9 cycles.
010: 15 cycles; 011: 30 cycles.
100: 43 cycles; 101:57 cycles.
RW
110: 73 cycles; 111: 241 cycles.
These bits are used to independently select the sample time
for each channel, and the channel configuration value must
remain constant during the sample cycle.
27 26 25 24
Reserved
11 10 9 8
81
23 22 21 20
7 6 5 4
SMP11[2:0]
Description
23 22 21 20
SMP7[2:0] SMP6[2:0]
7 6 5 4
SMP1[2:0]
Description
23 22 21 20
7 6 5 4
JOFFSETx[11:0]
http://wch.cn
19 18 17 16
SMP15[2:1]
3 2 1 0
SMP10[2:0]
Reset
value
0
0
19 18 17 16
SMP5[2:1]
3 2 1 0
SMP0[2:0]
Reset
value
0
19 18 17 16
3 2 1 0