Apb2 Peripheral Reset Register (Rcc_Apb2Prstr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[15:13] Reserved
12 PLLRDYIE
11 HSERDYIE
10 HSIRDYIE
9 Reserved
8 LSIRDYIE
7 CSSF
[6:5] Reserved
4 PLLRDYF
3 HSERDYF
2 HSIRDYF
1 Reserved
0 LSIRDYF

3.4.4 APB2 Peripheral reset register (RCC_APB2PRSTR)

Offset address: 0x0C
31 30 29 28
15 14 13 12
USAR
Rese Rese SPI1
T1
rved rved RST
RST
Bit Name
[31:15] Reserved
14 USART1RST
13 Reserved
12 SPI1RST
V1.3
0: No action.
RO Reserved
PLL-ready interrupt enable bit.
RW 1: Enable the PLL-ready interrupt.
0: Disable the PLL-ready interrupt.
HSE-ready interrupt enable bit.
RW 1: Enable HSE-ready interrupt.
0: Disable HSE-ready interrupt.
HSI-ready interrupt enable bit.
RW 1: Enable HSI-ready interrupt.
0: Disable HSI-ready interrupt.
RO Reserved
LSI-ready interrupt enable bit.
RW 1: Enable LSI-ready interrupt.
0: Disable LSI-ready interrupt.
Clock security system interrupt flag bit.
1: HSE clock failure, which generates a clock safety
RO interrupt CSSI.
0: No clock security system interrupt. Hardware set,
software write CSSC bit 1 cleared.
RO Reserved
PLL clock-ready lockout interrupt flag.
1: PLL clock lock generating interrupt.
RO
0: No PLL clock lock interrupt.
Hardware set, software write PLLRDYC bit 1 cleared.
HSE clock-ready interrupt flag.
1: HSE clock-ready interrupt generation.
RO
0: No HSE clock-ready interrupt.
Hardware set, software write HSERDYC bit 1 cleared.
HSI clock-ready interrupt flag.
1: HSI clock-ready interrupt generation.
RO
0: No HSI clock-ready interrupt.
Hardware set, software write HSIRDYC bit 1 cleared.
RO Reserved
LSI clock-ready interrupt flag.
1: LSI clock-ready interrupt generation.
RO
0: No LSI clock-ready interrupt.
Hardware set, software write LSIRDYC bit 1 cleared.
27 26 25 24
Reserved
11 10 9 8
ADC
TIM1 Reser
1
RST ved
RST
Access
RO Reserved
USART1 interface reset control.
RW
1: Reset module; 0: No effect.
RO Reserved
SPI1 interface reset control.
RW
1: Reset module; 0: No effect.
23 22 21
7 6 5
IOPD IOPC
Reserved
RST RST
Description
20
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20 19 18 17
4 3 2 1
Reser IOPA Reser
ved RST ved
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
AFIO
RST
0
0
0
0