Spi Status Register (Spi1_Statr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Control register 2
Bit Name
[15:8] Reserved
7 TXEIE
6 RXNEIE
5 ERRIE
[4:3] Reserved
2 SSOE
1 TXDMAEN
0 RXDMAEN

14.3.3 SPI Status register (SPI1_STATR)

Offset address: 0x08
15 14 13 12
Reserved
Bit Name
[15:8] Reserved
7 BSY
6 OVR
5 MODF
4 CRCERR
3 UDR
V1.3
Access
RO Reserved
Tx buffer empty interrupt enable bit. Setting this
RW bit allows an interrupt to be generated when TXE
is set.
RX buffer not empty interrupt enable bit. Used to
RW generate an interrupt request when the RXNE flag
is set.
Error interrupt enable bit. Setting this bit allows
RW interrupts to be generated when errors (CRCERR,
OVR, MODF) are generated.
RO Reserved
SS output enable bit. Disabling SS output can
work in multi-master mode.
RW
1: Enable the SS output.
0: Disable SS output in Master mode.
Tx buffer DMA enable bit.
1：Enable Tx buffer DMA.
RW
0：Disable Tx buffer DMA.
Rx buffer DMA enable bit.
1：Enable Rx buffer DMA.
RW
0：Disable Rx buffer DMA.
11 10 9 8
BSY OVR MODF
Access
RO Reserved
Busy flag. This flag is set and cleared by
hardware.
1：SPI is busy in communication or Tx buffer is
RO
not empty.
0：SPI (or I
Overrun flag. This flag is set by hardware and
reset by a software sequence.
RWO
1：Overrun occurred.
0：No overrun occurred.
Mode fault. This flag is set by hardware and reset
by a software sequence.
RO
1：Mode fault occurred.
0：No mode fault occurred.
CRC error flag. This flag is set by hardware and
reset by a software sequence.
1：CRC value received does not match the
RW0
SPI_RXCRCR value.
0：CRC
SPI_RXCRCR value.
Underrun flag. This flag is set by hardware and
reset by a software sequence.
R0
1：Underrun occurred.
0：No underrun occurred.
Description
7 6 5 4
CRC
ERR
Description
2 S) not busy.
value received
162
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Reset value
0
0
0
0
0
0
0
0
3 2 1
UDR CHSID TXE RXNE
Reset value
0
0
0
0
0
matches the
0
0