Reload Register; Status Register - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
4.3.3 Reload register (IWDG_RLDR)
Offset address: 0x08
15 14 13 12
Reserved
Bit Name
[15:12] Reserved
[11:0] RL
Note: This register will be reset in Standby mode.
4.3.4 Status Register (IWDG_STATR)
Offset address: 0x0C
15 14 13 12
Bit Name
[15:2] Reserved
1 RVU
0 PVU
Note: After the prescaler or reload value is updated, it is not necessary to wait for the RVU or PVU to reset,
and the following code can continue to be executed. (This write operation will continue to be executed to
completion even in low-power mode.)
V1.3
11 10 9 8
Access
RO Reserved
Counter reload value. Write 0x5555 to the KEY
before modifying this field.
When 0xAAAA is written to the KEY, the value
of this field will be loaded into the counter by
hardware, and the counter will then count
RW
decreasingly from this value.
Note: Before reading or writing the value of this
field, make sure the RVU bit in the IWDG_STATR
register is 0, otherwise reading or writing this field
is invalid.
11 10 9 8
Reserved
Access
RO Reserved
Reload value update flag bit. Hardware set or clear
0.
1: Reload value update is in progress.
RO 0: End of reload update (up to 5 LSI cycles).
Note: The reload value register IWDG_RLDR can
only be accessed read or write after the RVU bit is
cleared to 0.
Clock division factor update flag bit. Hardware set
or clear 0.
1: Clock division value update is in progress.
0: End of clock division value update (up to 5 LSI
RO
cycles).
Note: The crossover factor register IWDG_PSCR
can only be accessed read or write after the PVU
bit is cleared to 0.
7 6 5
RL [11:0]
Description
7 6 5
Description
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4 3 2 1
Reset value
0
FFFh
4 3 2 1
RVU PVU
Reset value
0
0
0
0
0