Usart Control Register 3 (Usart_Ctlr3) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
7 Reserved
6 LBDIE
5 LBDL
4 Reserved
[3:0] ADD

12.10.6 USART Control register 3 (USART_CTLR3)

Offset address: 0x14
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:11] Reserved
10 CTSIE
9 CTSE
8 RTSE
7 DMAT
6 DMAR
5 SCEN
4 NACK
3 HDSEL
2 IRLP
1 IREN
0 EIE
V1.3
1: The clock pulse of the last data bit is output to
the CK pin
Note: This bit cannot be modified after enabling
transmit.
RW Reserved
LIN break detection interrupt enable, this position
RW
bit enables interrupts caused by LBD.
LIN disconnect detection length, this bit is used to
select whether the disconnect detection is 11 bits
RW or 10 bits.
1: 11-bit disconnector detection.
0: 10-bit break character detection.
RW Reserved
Address of the USART node, this bit-field gives
the address of the USART node. This is used in
RW
multiprocessor
mode, for wake up with address mark detection.
27 26 25 24
Reserved
11 10 9 8
CTSI
CTSE RTSE
E
Access
RO Reserved
CTS interrupt enable bit, when this bit is set, an
RW
interrupt will be generated when CTS is set.
CTS enable bit, setting this bit will enable CTS
RW
flow control.
RTS enable bit, setting this bit will enable RTS
RW
flow control.
DMA transmit enable bit. This bit 1 uses DMA
RW
when transmitting.
DMA receive enable bit. This position 1 uses
RW
DMA on receive.
Smartcard mode enable bit, set to 1 to enable
RW
smart card mode.
Smartcard NACK enable bit, set this bit to send
RW
NACK in case of check error.
Half-duplex selection bit, set this bit to select half-
RW
duplex mode.
IrDA low-power bit, set this bit to enable low-
RW
power mode when IrDA is selected.
IrDA enable bit, set this bit to enable infrared
RW
mode.
Error interrupt enable bit, when set, generates an
RW interrupt if FE, ORE or NE is set provided that
DMAR is set.
communication
23 22 21
7 6 5
DMA DMA SCE NAC
T R N
Description
142
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0
0
0
0
0
during mute
20 19 18 17
4 3 2 1
HDS
IRLP IREN EIE
K EL
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
16
0