Compare Output Mode - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
of the compare capture host channel and clock source selection directly determines its function. The compare
capture channel is bidirectional and can operate in both input and output modes.
11.3.1 Input capture mode
The input capture mode is one of the basic functions of the timer. The principle of input capture mode is that
when a determined edge on the ICxPS signal is detected, a capture event is generated and the current value of
the counter is latched into the compare capture register (R16_TIMx_CHCTLRx). The CCxIF (in
R16_TIMx_INTFR) is set when a capture event occurs, and the corresponding interrupt or DMA is generated
if enabled. If the CCxIF is already set when a capture event occurs, the CCxOF bit is set. the CCxIF can be
cleared by software, or by hardware by reading the compare capture register. CCxOF is cleared by software.
An example of channel 1 to illustrate the steps to use the input capture mode is as follows.
1) Configure the CCxS domain to select the source of the ICx signal. For example, set it to 10b and select
TI1FP1 as the source of IC1, not using the default setting, the CCxS domain defaults to making the
comparison capture module the output channel.
2) Configure the ICxF domain to set the digital filter for the TI signal. The digital filter will sample the
signal at a determined frequency, a determined number of times, and then output a hop. This sampling
frequency and number of times is determined by ICxF.
3) Configure the CCxP bit to set the polarity of the TIxFPx. For example, keeping the CC1P bit low and
selecting rising edge jumps.
4) Configure the ICxPS domain to set the ICx signal to be the crossover factor between ICxPS. For example,
keeping ICxPS at 00b, without crossover.
5) Configure the CCxE bit to allow capturing the value of the core counter (CNT) into the compare capture
register. Set the CC1E bit.
6) Configure the CCxIE and CCxDE bits as needed to determine whether to allow enable interrupts or DMA.
This completes the comparison capture channel configuration.
When a captured pulse is input to TI1, the value of the core counter (CNT) is recorded in the compare capture
register, CC1IF is set, and the CCIOF bit is set when CC1IF has been set before. If the CC1IE bit is set, then
an interrupt is generated; if CC1DE is set, a DMA request is generated. An input capture event can be generated
by software by way of writing the event generation register (R16_TIMx_SWEVGR).

11.3.2 Compare output mode

The compare output mode is one of the basic functions of the timer. The principle of the compare output mode
is to output a specific change or waveform when the value of the core counter (CNT) agrees with the value of
the compare capture register. the OCxM field (in R16_TIMx_CHCTLRx) and the CCxP bit (in
R16_TIMx_CCER) determine whether the output is a definite high or low level or a level flip. The CCxIF bit
is also set when a compare coherent event is generated. If the CCxIE bit is pre-set, an interrupt will be
generated; if the CCxDE bit is pre-set, a DMA request will be generated.
To configure to compare output modes, proceed as follows.
1) Configuring the clock source and auto-reload value of the core counter (CNT).
2) Set the count value to be compared to the comparison capture register (R16_TIMx_CHxCVR).
3) Set the CCxIE bit if an interrupt needs to be generated.
4) Keep OCxPE at 0 to disable the preload register for the compare capture register.
5) Setting the output mode, setting the OCxM field and the CCxP bit.
6) Enable the output, setting the CCxE bit.
7) Setting the CEN bit to start the timer.
11.3.3 Forced output mode
The output pattern of the timer's compare capture channel can be forced by software to output a determined
level without relying on comparison of the compare capture register's shadow register with the core counter.
This is done by setting OCxM to 100b, which forces OCxREF to low, or by setting OCxM to 101b, which
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