WCH CH32V003 Series Reference Manual page 154

CH32V003 Reference Manual
10 AF
9 ARLO
8 BERR
7 TxE
6 RxNE
5 Reserved
4 STOPF
3 ADD10
2 BTF
1 ADDR
V1.3
received byte will be lost; when in send mode, no
new data is written to the data register, and the
same byte will be sent twice.
0: No overrun or underrun events.
Acknowledge failure bit. Cleared by software
writing 0, or by hardware when PE=0.
RW0
1：Acknowledge failure.
0：No acknowledge failure.
Arbitration lost bit. Cleared by software writing
0, or by hardware when PE=0.
RW0
1：Arbitration Lost detected.
0：No Arbitration Lost detected.
Bus error bit. Cleared by software writing 0, or by
hardware when PE=0.
RW0
1：No misplaced Start or Stop condition.
0：No misplaced Start or Stop condition.
Data register empty bit. Cleared by software
writing to the DR register or by hardware after a
start or a stop condition or when PE=0.
RO
1：Data register empty.
0：Data register not empty.
Data register not empty bit. Cleared by software
reading or writing the DR register or by hardware
when PE=0.
RO
1：Data register not empty.
0：Data register empty.
RO Reserved
Stop detection bit. Cleared by software reading
the SR1 register followed by a write in the CR1
register, or by hardware when PE=0
1：Set by hardware when a Stop condition is
RO
detected on the bus by the slave after an
acknowledge (if ACK=1).
0：No Stop condition detected.
10-bit header sent bit. Cleared by software
reading the SR1 register followed by a write in the
DR register of the second address byte, or by
RO
hardware when PE=0.
1：Master has sent first address byte.
0：No ADD10 event occurred.
Byte transfer finished bit. Cleared by software
reading SR1 followed by either a read or write in
the DR register or by hardware after a start or a
stop condition in transmission or when PE=0.
1：Data byte
RO NOSTRETCH=0: when sending, when a new data
is sent and the data register has not yet been
written with new data; when receiving, when a
new byte is received but the data register has not
yet been read.
0：Data byte transfer not done.
Address sent /matched bit. This bit is cleared by
software reading SR1 register followed reading
SR2, or by hardware when PE=0.
RW0
In Master mode:
1：End of address transmission.
addressing, the bit is set after the ACK of the 2nd
154
transfer succeeded.
For 10-bit
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0
0
0
0
0
0
0
0
When
0
0