Table 5-1 Description Of The Entire Lin Communication Control Registers And Setting Values - Fujitsu F2MC-8FX Series User Manual

Table 5-1 Description of the entire LIN communication control registers and setting values

Register name Set value (contents)
SCR_PEN 0 (no parity)
SCR_P 0 (even parity)
SCR_SBL 0 (1 bit)
SCR_CL 1 (8 bit)
SCR_AD 0 (data frame)
SCR_CRE 1 (clear flag)
SCR_RXE 0 (Receive prohibited)
SCR_TXE 1 (Transmit enabled)
SMR_MD1 1 (mode 3)
SMR_MD0 1 (asynchronous LIN mode)
SMR_OTO 0 (use external clock)
SMR_EXT 0 (use baud rate generator)
SMR_REST 0
1 (LIN-UART reset)
SMR_UPCL
0 (general I/O port or LIN-UART clock input
SMR_SCKE
pin)
SMR_SOE 1 (LIN-UART serial data output pin)
0 (LSB first (transfer from least significant
SSR_BDS
bit))
SSR_RIE 1 (Receive interrupt enable)
SSR_TIE 0 (Transmit interrupt prohibited)
0 (LIN synch break detection interrupt
ESCR_LBIE
prohibited)
ESCR_LBD 0 (LIN synch break detection flag clear)
ESCR_LBL1 0
ESCR_LBL0 0 (13 bits)
ESCR_SOPE 0 (serial output pin access prohibited)
ESCR_SIOP 0
ESCR_CC0 0
ESCR_SCES 0
Explanation
Parity authorization bit
Parity selection bit
Stop bit length selection bit
Data length selection bit
Address / data format selection bit
Clear reception error flag bit
Receive prohibition enable bit
Transmit enable bit
Operation mode selection bit
1-to-1 external input enable bit
External serial clock source selection bit
Reload counter restart bit
Programmable clear bit
(LIN-UART software reset)
Serial clock output enable bit
Serial data output enable bit
Transfer direction selection bit
Receive interrupt request enable
Transmit interrupt request enable
LIN synch break detection interrupt enable
bit
LIN synch break detection flag bit
LIN synch break length selection bit
Serial output pin direct access enable bit
Serial I/O pin direct access enable bit
Continuous clock output enable bit
Sampling clock edge selection bit
90
AN07-00200-03E