Full Status Check - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

18.8.4 Full Status Check

If an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to "1", indicating a specific error.
Therefore, execution results can be comfirmed by verifying these status bits (full status check).
Table 18.7 lists errors and FMR0 register state. Figure 18.15 shows a flow chart of the full status check
and handling procedure for each error.
Table 18.7 Errors and FMR0 Register Status
FMR0 Register
(SRD register)
status
FMR07 FMR06
(SR5) (SR4)
1 1
1 0
0 1
NOTE:
1. The flash memory enters read array mode by writing command code 'xxFF
of these commands. The command code written in the first bus cycle becomes invalid.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
Error
Command • An incorrect commands is written
sequence error • A value other than 'xxD0
bus cycle of the block erase command
• When the block erase command is executed on an protected block
• When the program command is executed on protected blocks
Erase error • The block erase command is executed on an unprotected block
but the program operation is not successfully completed
Program error • The program command is executed on an unprotected block but
the program operation is not successfully completed
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Error occurrence condition
' or 'xxFF ' is written in the second
16 16
(1)
16
18. Flash Memory Version
' in the second bus cycle