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17.8.4 Full Status Check
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to "1", indicating occur-
rence of each specific error. Therefore, execution results can be verified by checking these status bits
(full status check). Table 17.8.4.1 shows errors and the status of FMR0 register. Figure 17.8.4.1
shows a flow chart of the full status check and handling procedure for each error.
Table 17.8.4.1. Errors and FMR0 Register Status
FMR0 register
(SRD register)
status
FMR07
FMR06
(SR5)
(SR4)
1
1
1
0
0
1
NOTE:
1. The flash memory enters read array mode by writing command code 'xxFF
cycle of these commands. The command code written in the first bus cycle becomes invalid.
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2
0 .
0
F
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1 .
, 5
2
0
0
7
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0
9
B
0
2
0
2
0 -
2
0
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Error
Command
• When any commands are not written correctly
sequence error • A value other than 'xxD0
bus cycle of the block erase command
• When the block erase command is executed on protected blocks
• When the program command is executed on protected blocks
Erase error
• When the block erase command is executed on unprotected
blocks but the blocks are not automatically erased correctly
Program error
• When the program command is executed on unprotected blocks
but the blocks are not automatically programmed correctly.
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Error occurrence condition
17. Flash Memory Version
' or 'xxFF
' is written in the second
16
16
(1)
' in the second bus
16
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