Full Status Check - Renesas M16C FAMILY Hardware Manual

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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group

17.4.5 Full Status Check

When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to "1", indicating occur-
rence of each specific error. Therefore, execution results can be verified by checking these status bits
(full status check). Table 17.6 lists errors and FMR0 register status. Figure 17.11 shows a full status
check flowchart and the action to be taken when each error occurs.
Table 17.6 Errors and FMR0 Register Status
FRM00 register
(status register)
status
FMR07 FMR06
(SR5) (SR4)
1 1
1 0
0 1
Notes:
1. Writing 'FF ' in the second bus cycle of these commands places the microcomputer in read array
16
mode, and the command code written in the first bus cycle is nullified.
Rev.0.91 2003 Sep 08
Error
Command • When any command is not written correctly
sequence error • When invalid data was written other than those that can be writ-
ten in the second bus cycle of the Block Erase command (i.e.,
other than 'D0
Erase error • When the Block Erase command was executed but not automati-
cally erased correctly
Program error • When the Program command was executed but not automatically
programmed correctly.
page 163 of 184
Error occurrence condition
1
' or 'FF ')
16 16
17.4 CPU Rewrite Mode