Condition Register Logical Instructions; Register Management Instructions; System Linkage Instructions; Processor Synchronization Instruction - IBM PPC440X5 CPU Core User Manual

Preliminary

2.4.3.1 Condition Register Logical Instructions

These instructions perform logical operations on a specified pair of bits in the CR, placing the result in
another specified bit. The benefit of these instructions is that they can logically combine the results of several
comparison operations without incurring the overhead of conditional branching between each one. Software
performance can significantly improve if multiple conditions are tested at once as part of a branch decision.
Table 2-14 lists the condition register logical instructions in the PPC440x5.

2.4.3.2 Register Management Instructions

These instructions move data between the GPRs and control registers in the PPC440x5.
Table 2-15 lists the register management instructions in the PPC440x5.

2.4.3.3 System Linkage Instructions

These instructions invoke supervisor software level for system services, and return from interrupts.
Table 2-16 lists the system linkage instructions in the PPC440x5.

2.4.3.4 Processor Synchronization Instruction

Tne processor synchronization instruction,
the isync before allowing any context changes as a result of any instructions that follow the
ally, all instructions that follow the
the instructions that precede the
isync .
synchronizing effect of
prgmodel.fm.
September 12, 2002

Table 2-14. Condition Register Logical Instructions

crand crnor
crandc cror
creqv crorc
crnand crxor

Table 2-15. Register Management Instructions

CR DCR
mcrf mfmsr
mcrxr mfdcr mtmsr
mfcr mtdcr wrtee
mtcrf wrteei

Table 2-16. System Linkage Instructions

rfi
rfci
rfmci
sc
isync , forces the processor to complete all instructions preceding
isync will execute within the context established by the completion of all
isync . See Synchronization on page 82 for more information on the
MSR SPR
mfspr
mtspr
User's Manual
PPC440x5 CPU Core
isync . Addition-
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