Figure 6-1. Pipelined Execution Unit; Figure 6-2. Superscalar/Pipeline Diagram - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
• 64-bit floating-point unit (FPU)
• Load/store unit (LSU)
• System register unit (SRU)
Figure 6-1 represents a generic pipelined execution unit.

Figure 6-1. Pipelined Execution Unit

The 750GX can retire two instructions in every clock cycle. In general, the 750GX processes instructions in
four stages—fetch, decode/dispatch, execute, and complete as shown in Figure 6-2. Note that the example of
a pipelined execution unit in Figure 6-1 is similar to the 3-stage FPU pipeline in Figure 6-2.

Figure 6-2. Superscalar/Pipeline Diagram

BPU
SRU
Instruction Timing
Page 212 of 377
Stage 1
Clock 0 Instruction A
Instruction B
Clock 1
Instruction C
Clock 2
Clock 3 Instruction D
Decode/Dispatch
FPU1
FPU2
FPU3
Complete (Write-back)
Stage 2 Stage 3
—
Instruction A
Instruction B Instruction A
Instruction C Instruction B
Maximum 4-instruction fetch per
Fetch
clock cycle
Maximum 3-instruction dispatch per
clock cycle (includes one branch
instruction)
IU1 IU2
Maximum 2-instruction completion per
clock cycle
—
—
Execute Stage
LSU1
LSU2
gx_06.fm.(1.2)
March 27, 2006