Exception Syndrome Register (Esr); Figure 6-9. Interrupt Vector Prefix Register (Ivpr); Figure 6-10. Exception Syndrome Register (Esr) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
0
Figure 6-9. Interrupt Vector Prefix Register (IVPR)
0:15 IVP Interrupt Vector Prefix
16:31 Reserved

6.4.11 Exception Syndrome Register (ESR)

The ESR provides a syndrome to differentiate between the different kinds of exceptions that can generate the
same interrupt type. Upon the generation of one of these types of interrupt, the bit or bits corresponding to the
specific exception that generated the interrupt is set, and all other ESR bits are cleared. Other interrupt types
do not affect the contents of the ESR. Figure 6-10 on page 172 provides a summary of the fields of the ESR
along with their definitions. See the individual interrupt descriptions under Interrupt Definitions on page 175
for an explanation of the ESR settings for each interrupt type, as well as a more detailed explanation of the
function of certain ESR fields.
The ESR can be written from a GPR using
MCI PIL PTR
0 1 3 4 5 6
PPR

Figure 6-10. Exception Syndrome Register (ESR)

Machine Check—Instruction Fetch Exception
0 Instruction Machine Check exception did not
0 MCI
occur.
1 Instruction Machine Check exception occurred.
1:3 Reserved
Program Interrupt—Illegal Instruction Exception
0 Illegal Instruction exception did not occur.
4 PIL
1 Illegal Instruction exception occurred.
Program Interrupt—Privileged Instruction Excep-
tion
5 PPR
0 Privileged Instruction exception did not occur.
1 Privileged Instruction exception occurred.
Program Interrupt—Trap Exception
0 Trap exception did not occur.
6 PTR
1 Trap exception occurred.
Page 172 of 589
IVP
mtspr , and can be read into a GPR using mfspr .
ST
AP
7 8 9 10 11 12 13 14 15 16
FP DLK PUO
15 16
BO
PIE
This is an implementation-dependent field of the
ESR and is not part of the PowerPC Book-E Archi-
tecture.
Preliminary
31
PCRE PCRF
26 27 28 29 31
PCMP
intrupts.fm.
September 12, 2002