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PSW by the number of halfword locations
indicated in the ILC, the address originally
appearing in the PSW may be obtained.
2. When a page-access exception is recognized
while fetching an instruction, including the
target instruction of EXECUTE, the ILC is
arbitrarily set to 1, 2, or 3. In this case, the
operation is nullified, and the instruction
address is not incremented.
The ILC is not necessarily related to the first
two bits of the instruction when the first halfword
of an instruction can be fetched but an access
exception is recognized on fetching the second or
third halfword. The ILC may be arbitrarily set to
1, 2, or 3 in these cases. The instruction address is
or is not updated, as described in situations 1 and 2
above.
When any exceptions other than page access are
encountered on fetching the target instruction of
EXECUTE, the ILC is 2.
Programming Notes
1. A nonzero instruction-length code for a
program interruption indicates the number of
halfword locations by which the instruction
address in the old PSW must be reduced to
obtain the address of the last instruction
executed, unless one of the following situations
exists:
a.
The interruption is caused by a page-access
exception.
b. An interruption for a PER event occurs
before the execution of an interruptible
instruction is ended.
c.
The interruption is caused by a PER event
due to LOAD PSW or a branch or linkage
instruction, including SUPERVISOR
CALL.
d. The interruption is caused by an access
exception encountered in fetching an
instruction, and the instruction address has
been introduced into the PSW by a means
other than sequential operation (by a
branch instruction, LOAD PSW, or an
interruption) .
e.
The interruption is caused by a specification
exception because of an odd instruction
address.
For situations a and b above, the instruction
address in the PSW is not incremented, and the
instruction designated by the instruction
address is the same as the last one executed.
These two are the only cases in which the
6-6
IBM 4300 Processors Principles of Operation
instruction address in the old PSW identifies
the instruction causing the exception.
For situations c, d, and e, the instruction
address has been replaced as part of the
operation, and the address of the last
instruction executed cannot be calculated using
the one appearing in the old PSW.
2. When a PER event is indicated, bit 8 in the
interruption code is one, the PER address in the
word at location 152 identifies the location of
the instruction causing the interruption, and the
instruction-length code (ILC) is redundant.
Similarly, the ILC is redundant when the
operation is nullified, since in this case the
instruction address in the PSW is not
incremented. If the ILC value is required in
this case, it can be derived from the operation
code of the instruction identified by the old
PSW.
Exceptions Associated with the PS W
Exceptions associated with erroneous information
in the current PSW may be recognized when the
information is introduced into the PSW or may be
recognized as part of the execution of the next
instruction. Errors in the PSW which are
specification-exception conditions are called
PSW -format errors.
Early Exception Recognition
A program interruption for a specification
exception occurs immediately after the PSW
becomes active if a one is introduced into an
unassigned bit position of an EC-mode PSW (that
is, bit positions 0,2-5, 16, 17, or 24-39).
The interruption takes place regardless of
whether the wait state is specified. If the invalid
PSW causes the CPU to become enabled for a
pending 1/0, external, or machine-check
interruption, the program interruption is taken
instead, and the pending interruption is subject to
the mask bits of the new PSW introduced by the
program interruption.
When the execution of LOAD PSW or an
interruption introduces a PSW with one of the
above error conditions, the instruction-length code
is set to 0, and the newly introduced PSW, except
for the interruption code and the instruction-length
code in the BC mode, is stored unmodified as the
old PSW. When one of the above error conditions
is introduced by execution of SET SYSTEM MASK
or STORE THEN OR SYSTEM MASK, the
instruction-length code is set to 2, and the
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