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User's Manual
IBM PowerPC 750GX and GL RISC Microprocessor
4.5.8 Floating-Point Unavailable Exception (0x00800)
The floating-point unavailable exception is implemented as defined in the PowerPC Architecture. A floating-
point unavailable exception occurs when no higher-priority exception exists, an attempt is made to execute a
floating-point instruction (including floating-point load, store, or move instructions), and the floating-point
available bit in the MSR is disabled, (MSR[FP] = 0). Register settings for this exception are described in
Chapter 6, "Exceptions" in the PowerPC Microprocessor Family: The Programming Environments Manual.
When a floating-point unavailable exception is taken, instruction fetching resumes at offset 0x00800 from the
physical base address indicated by MSR[IP].
4.5.9 Decrementer Exception (0x00900)
The decrementer exception is implemented in the 750GX as it is defined by the PowerPC Architecture. The
decrementer exception occurs when no higher-priority exception exists, a decrementer exception condition
occurs (for example, the Decrementer Register has completed decrementing), and MSR[EE] = 1. In the
750GX, the Decrementer Register is decremented at one fourth the bus clock rate. Register settings for this
exception are described in Chapter 6, "Exceptions" in the PowerPC Microprocessor Family: The Program-
ming Environments Manual.
When a decrementer exception is taken, instruction fetching resumes at offset 0x00900 from the physical
base address indicated by MSR[IP].
4.5.10 System Call Exception (0x00C00)
A system-call exception occurs when a System Call (sc) instruction is executed. In the 750GX, the system
call exception is implemented as it is defined in the PowerPC Architecture. Register settings for this exception
are described in Chapter 6, "Exceptions" in the PowerPC Microprocessor Family: The Programming Environ-
ments Manual.
When a system call exception is taken, instruction fetching resumes at offset 0x00C00 from the physical base
address indicated by MSR[IP].
4.5.11 Trace Exception (0x00D00)
The trace exception is taken if MSR[SE] = 1 or if MSR[BE] = 1 and the currently completing instruction is a
branch. Each instruction considered during trace mode completes before a trace exception is taken.
Implementation Note: The 750GX processor diverges from the PowerPC Architecture in that it does not
take trace exceptions on the isync instruction.
When a trace exception is taken, instruction fetching resumes at offset 0x00D00 from the base address indi-
cated by MSR[IP].
4.5.12 Floating-Point Assist Exception (0x00E00)
The optional floating-point assist exception defined by the PowerPC Architecture is not implemented in the
750GX.
gx_04.fm.(1.2)
Exceptions
March 27, 2006
Page 171 of 377
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