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Table 8-6. Aligned Data Transfers (32-Bit Bus Mode)
Transfer Size
TSIZ0
0
0
Half word
0
0
1
Word
1
0
Double word
Second beat
0
Note:
A:
Byte lane used
—:
Byte lane not used
x:
Byte lane not used in 32-bit bus mode
Misaligned data transfers when the 750GX is configured with a 32-bit data bus operate in the same way as
when configured with a 64-bit data bus, with the exception that only the DH[0–31] data bus is used. See
Table 8-7 on page 299 for an example of a 4-byte misaligned transfer starting at each possible byte address
within a double word.
Table 8-7. Misaligned 32-Bit Data-Bus Transfer (4-Byte Examples)
Transfer Size
(Four Bytes)
Aligned
Misaligned—first access
second access
Misaligned—first access
second access
Misaligned—first access
second access
Aligned
Misaligned—first access
second access
Misaligned—first access
second access
Misaligned—first access
second access
Note:
A:
Byte lane used
—:
Byte lane not used
x:
Byte lane not used in 32-bit bus mode
gx_08.fm.(1.2)
March 27, 2006
TSIZ1
TSIZ2
A[29–31]
1
0
000
1
0
010
1
0
100
1
0
110
0
0
000
0
0
100
0
0
000
0
0
000
TSIZ[0–2]
A[29–31]
1 0 0
0 0 0
0 1 1
0 0 1
0 0 1
1 0 0
0 1 0
0 1 0
0 1 0
1 0 0
0 0 1
0 1 1
0 1 1
1 0 0
1 0 0
1 0 0
0 1 1
1 0 1
0 0 1
0 0 0
0 1 0
1 1 0
0 1 0
0 0 0
0 0 1
1 1 1
0 1 1
0 0 0
IBM PowerPC 750GX and 750GL RISC Microprocessor
(Page 2 of 2)
Data-Bus Byte Lanes
0
1
2
A
A
—
—
—
A
A
A
—
—
—
A
A
A
A
A
A
A
A
A
A
A
A
A
Data-Bus Byte Lanes
0
1
2
A
A
A
A
A
A
—
—
—
—
A
A
A
—
—
—
—
A
A
A
A
A
A
—
A
A
A
—
—
—
—
A
A
A
—
—
—
—
A
A
A
User's Manual
3
4
5
6
—
x
x
x
A
x
x
x
—
x
x
x
A
x
x
x
A
x
x
x
A
x
x
x
A
x
x
x
A
x
x
x
3
4
5
6
A
x
x
x
A
x
x
x
—
x
x
x
A
x
x
x
x
x
x
x
A
x
x
x
—
x
x
x
A
x
x
x
A
x
x
x
—
x
x
x
A
x
x
x
—
x
x
x
A
x
x
x
—
x
x
x
Bus Interface Operation
Page 299 of 377
7
x
x
x
x
x
x
x
x
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
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