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PSW specifies the EC or BC mode. In both
modes, the link information is in the format of
the rightmost 32 bit positions of the BC-mode
PSW.
BRANCH ON CONDITION
BCR
o
8
12
15
BC
M1~02(X2~B2)
[RX]
'47'
I
M1
I
X2
I
B2
02
o
8
12
16
20
31
The instruction address in the current PSW is
replaced by the branch address if the condition
code has one of the values specified by M
1 ;
otherwise, normal instruction sequencing proceeds
with the updated instruction address.
In the RX format, the second-operand address is
used as the branch address. In the RR format, bits
8-31 of the general register specified by R
z
are
used as the branch address; however, when the R
z
field contains zeros, the operation is performed
without branching.
The M
1
field is used as a four-bit mask. The
four condition codes (0, 1,2, and 3) correspond,
left to right, with the four bits of the mask, as
follows:
Mask
Condition
Instruction
Position
Code
Bit
Value
0
8
8
1
9
4
2
10
2
3
11
1
The current condition code is used to select the
corresponding mask bit.
If
the mask bit selected by
the condition code is one, the branch is successful.
If
the mask bit selected is zero, normal instruction
sequencing proceeds with the next sequential
instruction.
When the Ml and R
z
fields of BCR are all ones
and all zeros, respectively, a serialization function
is performed. CPU operation is delayed until all
previous accesses by this CPU to storage have been
completed, as observed by channels and other
CPUs. No subsequent instructions or their
operands are accessed by this CPU until the
execution of this instruction is completed.
Condition Code: The code remains unchanged.
Program Exceptions: None.
Programming Notes
1.
An example of the use of BRANCH ON
CONDITION is given in Appendix A.
2. When a branch is to depend on more than one
condition, the pertinent condition codes are
specified in the mask as the sum of their mask
position values. A mask of 12, for example,
specifies that a branch is to be made when the
condition code is 0 or 1.
3. When all four mask bits are zero or when the
R
z
field in the RR format contains zero, the
branch instruction is equivalent to a
no-operation. When all four mask bits are
ones, that is, the mask value is 15, the branch is
unconditional unless the R
z
field in the RR
format is zero.
4. Execution of BCR 15,0 (that is, an instruction
with a value of 07FO hex) may result in
significant performance degradation. To ensure
optimum performance, the program should
avoid use of BCR 15,0 except in cases when
the serialization function is actually required.
5. Note that the relation between the RR and RX
formats in branch-address specification is not
the same as in operand-address specification.
For branch instructions in the RX format, the
branch address is the address specified by X
z ,
B
z ,
and D
z ;
in the RR format, the branch
address is contained in the register specified by
R
z .
For operands, the address specified by X
z ,
B
z ,
and D
z
is the operand address, but the
register specified by R
z
contains the operand
itself.
BRANCH ON COUNT
BCTR
[RR]
'06'
I
R1
I
R2
o
8
12
15
Chapter 7. General Instructions
7-9
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