Chapter 1: Rocketio X Transceiver Overview; Basic Architecture And Capabilities; Table 1-1: Number Of Rocketio X Cores Per Device Type - Xilinx RocketIO X User Manual

R
RocketIO X Transceiver Overview

Basic Architecture and Capabilities

Note:
silicon. For Step 0 silicon, see the Errata for special considerations.
The RocketIO X block diagram is illustrated in
Virtex-II Pro X FPGA has between 8 and 20 transceiver modules, as shown in

Table 1-1: Number of RocketIO X Cores per Device Type

Definitions:
•
•
The transceiver module is designed to operate at any serial bit rate in the range of
2.488 Gb/s to 10.3125 Gb/s per channel, including the specific bit rates used by the
communications standards listed in
are set appropriately in the GT10 primitives.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
The definitions, descriptions, and recommendations in this user guide reflect Step 1
Device
XC2VPX20
XC2VPX70
Attribute – An attribute is a control parameter to configure the RocketIO X
transceiver. There are both primitive ports (traditional I/O ports for control and
status) and transceiver attributes. Transceiver attributes are also controls to the
transceiver that regulate data widths and encoding rules, but controls that are
configured as a group in "soft" form through the invocation of a primitive.
GT10 Primitive – A primitive is a pre-designed collection of attribute values that
accomplish a known data rate, encoding type, data width, etc. A single primitive
invocation, for example, OC-192 mode which configures all the dozens of pertinent
attributes to their correct values in a single step.
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Figure 1-1. Depending on the device, a
RocketIO X Cores
Table 1-2, page 27. Data-rate specific attribute settings
Chapter 1
Table 1-1.
8
20
25