Basic Architecture And Capabilities - Xilinx RocketIO User Manual

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RocketIO Transceiver Overview

Basic Architecture and Capabilities

The RocketIO transceiver is based on Mindspeed's SkyRail™ technology.
page
are available on a single Virtex-II Pro FPGA, depending on the part being used.
shows the RocketIO cores available by device.
Table 1-1: Number of RocketIO Cores per Device Type
The transceiver module is designed to operate at any serial bit rate in the range of
600 Mb/s to 3.125 Gb/s per channel, including the specific bit rates used by the
communications standards listed in
the transceiver, as the operating frequency is implied by the received data, the reference
clock applied, and the SERDES_10B attribute (see
Table 1-2: Communications Standards Supported by RocketIO Transceiver
Mode
Fibre Channel
Gbit Ethernet
(2)
PCI Express
XAUI (10-Gbit Ethernet)
XAUI (10-Gbit Fibre Channel)
Infiniband
Aurora (Xilinx protocol)
Custom Mode
Notes:
1. One channel is considered to be one transceiver.
2. Out-of-Band (OOB) signals are not supported with the transceiver.
3. Supported with the GT_CUSTOM primitive. Certain attributes must be modified to comply with the XAUI 10GFC specifications,
including but not limited to CLK_COR_SEQ and CHAN_BOND_SEQ.
4. Bit rate is possible with the following topology specification: maximum 6" FR4 and one Molex 74441 connector.
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
22, depicts an overall block diagram of the transceiver. Up to 20 transceiver modules
Device RocketIO Cores
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
(3)
www.xilinx.com
Device
4 XC2VP40
4 XC2VP50
8 XC2VP70
8 XC2VP100
8
Table 1-2. The serial bit rate need not be configured in
Table
Channels
(1)
(Lanes)
1
1
1
4
4
1, 4, 12
1, 2, 3, 4,...
1, 2, 3, 4,...
Chapter 1
Figure 1-1,
Table 1-1
RocketIO Cores
0 or 12
0 or 16
16 or 20
0 or 20
1-3).
I/O Bit Rate
(Gb/s)
1.06
2.12
1.25
2.5
3.125
(4)
3.1875
2.5
0.600 – 3.125
0.600 – 3.125
21