Basic Architecture And Capabilities - Xilinx RocketIO User Manual

R
RocketIO Transceiver Overview

Basic Architecture and Capabilities

The RocketIO transceiver is based on Mindspeed's SkyRail™ technology.
depicts an overall block diagram of the transceiver. Up to 20 transceiver modules are available on a
single Virtex-II Pro FPGA, depending on the part being used.
available by device.
Table 1-1: Number of RocketIO Cores per Device Type
The transceiver module is designed to operate at any serial bit rate in the range of 600 Mb/s to
3.125 Gb/s per channel, including the specific bit rates used by the communications standards listed
in
is implied by the received data, the reference clock applied, and the SERDES_10B attribute (see
Table
Table 1-2: Communications Standards Supported by RocketIO Transceiver
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
Device RocketIO Cores
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
Table 1-2. The serial bit rate need not be configured in the transceiver, as the operating frequency
1-3).
Mode
Fibre Channel
Gbit Ethernet
XAUI (10-Gbit Ethernet)
XAUI (10-Gbit Fibre Channel)
Infiniband
Aurora (Xilinx protocol)
Custom Mode
Notes:
1. One channel is considered to be one transceiver.
2. Supported with the GT_CUSTOM primitive. Certain attributes must be modified to comply with the XAUI
10GFC specifications, including but not limited to CLK_COR_SEQ and CHAN_BOND_SEQ.
3. Bit rate is possible with the following topology specification: maximum 6" FR4 and one Molex 74441 connector.
Device
4 XC2VP40
4 XC2VP50
8 XC2VP70
8 XC2VP100
8
Channels
(Lanes)
(2)
1, 4, 12
1, 2, 3, 4, ...
1, 2, 3, 4, ...
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Chapter 1
Figure 1-1, page
Table 1-1 shows the RocketIO cores
RocketIO Cores
0 or 12
0 or 16
16 or 20
0 or 20
I/O Bit Rate
(1)
(Gb/s)
1.06
1
2.12
1 1.25
4 3.125
4 3.1875
0.600 – 3.125
0.600 – 3.125
23,
(3)
2.5
21