Basic Architecture And Capabilities; Chapter 2: Rocketio Transceiver Overview; Table 2-1: Rocketio Cores; Table 2-2: Communications Standards Supported By Rocketio Transceiver - Xilinx RocketIO User Manual

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RocketIO Transceiver Overview

Basic Architecture and Capabilities

The RocketIO transceiver is based on Mindspeed's SkyRail™ technology.
page
are available on a single Virtex-II Pro FPGA, depending on the part being used.
shows the RocketIO cores available by device.

Table 2-1: RocketIO Cores

The transceiver module is designed to operate at any serial bit rate in the range of
622 Mb/s to 3.125 Gb/s per channel, including the specific bit rates used by the
communications standards listed in
the transceiver, as the operating frequency is implied by the received data, the reference
clock applied, and the SERDES_10B attribute

Table 2-2: Communications Standards Supported by RocketIO Transceiver

UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
16, depicts an overall block diagram of the transceiver. Up to 24 transceiver modules
Device
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
Mode
Fibre Channel
Gbit Ethernet
XAUI (10-Gbit Ethernet)
Infiniband
Aurora (Xilinx protocol)
Custom Mode
Notes:
1. One channel is considered to be one transceiver.
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RocketIO Cores
4
4
8
8
8
Table 2-2. The serial bit rate need not be configured in
(Table 2-3, page
Channels
(Lanes)
1
1
4
1, 4, 12
1, 2, 3, 4, ...
1, 2, 3, 4, ...
1-800-255-7778
Chapter 2
Figure 2-1,
Device RocketIO Cores
XC2VP40
XC2VP50
XC2VP70
XC2VP100
XC2VP125
16).
I/O Bit Rate
(1)
(Gb/s)
1.06
2.12
1.25
3.125
2.5
0.622 – 3.125
0.622 – 3.125
Table 2-1
0 or 12
0 or 16
20
0 or 20
0, 20, or 24
15