Model Considerations; Simulation Models; Smartmodels; Hspice - Xilinx RocketIO X User Manual

Model Considerations

Model Considerations
When running with the functional SWIFT model, users need to note that the model
correctly mimics the startup times required for the PMA. However, since the startup time
is in most cases greater than 10 µs, it is recommended that the complete model be used to
ensure correct system operation.
There are two components that delay the startup of the PMA. The first is the power-up
sequence within the PCS, which brings up PMA bias circuits in an orderly and predictable
manner. The second is the PMA itself, which has a long power-up cycle. For more
information on PMA power up, refer to
Given a reference clock with period t, the equation for computing the startup time is:
where the result and t are in nanoseconds.
When working with the model, observe the following suggestions:
1.
2.
3.
4.

Simulation Models

SmartModels

SmartModels are encrypted versions of the actual HDL code. These models allow the user
to simulate the actual functionality of the design without having access to the code itself.
A simulator with SmartModel capability is required to use SmartModels. See
Record 15501

HSPICE

HSPICE is an analog design model that allows simulation of the RX and TX high-speed
transceiver. To obtain these HSPICE models, go to the SPICE Suite Access web page at:
http://support.xilinx.com/support/software/spice/spice-request.htm.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
Time to startup = 10000*t +5000
After applying the reference clock and deasserting resets, TXOUTCLK should be
defined and oscillating. If TXOUTCLK is undefined, most likely the circuit is within
the instability period.
Note that in 64/66 protocols some periods for the reference clock results in a non-
integer multiple between the two clock domains on either side of the FIFOs. The ratio
must be exactly 64/66, or data is "lost" in the simulation due to rounding error. An
example of a good period for the reference clock in mode 6_32 would be 1.6 ns, which
results in a fabric period of 3.3 ns (the average is really three pulses of 3.2 ns followed
by one of 3.6 ns) and a PMA interface period of 3.2 ns. This ratio of 3.3/3.2 is exactly
proportional to 66/64, which meets the requirement.
If you are having problems passing data, try to put the model into loopback. Make sure that
TXOUTCLK and RXRECCLK are not undefined. If RXRECCLK is undefined, either the
clock data recovery circuit has not locked, or the input data is undefined.
Many signals in the design must be configured properly for the design to work. Be sure to
double check all resets to make sure they are in the correct state.
for information on how to install the SmartModels.
www.xilinx.com
1-800-255-7778
Appendix C, "PMA Attribute Programming Bus."
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Solution
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