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R
Table 40. DVOC Interface Package Lengths
Signal
DVOCBLANK#
DVOCCLK
DVOCCLK#
DVOCD[0]
DVOCD[1]
DVOCD[2]
DVOCD[3]
DVOCD[4]
DVOCD[5]
DVOCD[6]
DVOCD[7]
DVOCD[8]
DVOCD[9]
DVOCD[10]
DVOCD[11]
DVOCFLDSTL
DVOCHSYNC
DVOCVSYNC
7.3.2.4.
DVOB and DVOC Port Termination
The DVO interface does not require external termination.
7.3.3.
DVOB and DVOC Assumptions, Definitions, and Specifications
The source synchronous solution space consists of all designs in which the flight time mismatch
between a strobe and its associated data is less than the total allowable skew:
= T
T
skew
flightdata
Where T
flightdata
respectively.
The DVO physical interface is a point-to-point topology using 1.5-V signaling. The DVO uses a 165-
MHz clock.
The flight time skew simulations simulate all parameters that could cause a skew between two signals,
including motherboard and add-in card line lengths, effective capacitance in the buffer models, crosstalk
on each of the different interconnect combinations, data pattern dependencies, and ISI induced skews.
122
Pin Number
L3
J3
J2
K5
K1
K3
K2
J6
J5
H2
H1
H3
H4
H6
G3
H5
K6
L5
- T
flightstrobe
and T
are the driver-pad-to-receiver-pin flight times of the data and the strobe
flightstrobe
®
®
Intel
852GME, Intel
852GMV and Intel
Integrated Graphics Display Port
Package Length (mils)
541
601
675
489
692
622
685
536
518
720
771
649
625
521
762
566
491
440
®
852PM Chipset Platforms Design Guide
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