Figure 362. Transmission Bit Order; Figure 363. Transmission With No Collision - ST STM32F405 Reference Manual

RM0090
UDP or ICMP header is not modified. For the second error type, still, the calculated
checksum is inserted into the corresponding header field.
MII/RMII transmit bit order
Each nibble from the MII is transmitted on the RMII a dibit at a time with the order of dibit
transmission shown in
followed by higher order bits (D2 and D3).
MII/RMII transmit timing diagrams
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
MII_COL
Ethernet (ETH): media access control (MAC) with DMA controller
Figure 362. Lower order bits (D1 and D0) are transmitted first

Figure 362. Transmission bit order

LSB
MII_TXD[3:0]
MSB
Nibble stream

Figure 363. Transmission with no collision

PR
MII_CS
Low
LSB MSB
D0 D1
D0
D1
D2
D3
EA MB LE
RM0090 Rev 18
Bibit stream
ai15632
ai15631
1143/1749
1239