Figure 358. Clock Scheme - ST STM32F405 Reference Manual

RM0090
MII/RMII internal clock scheme
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s
operations is described in
MII_TX_CLK as AF
(25 MHz or 2.5 MHz)
MII_RX_CLK as AF
(25 MHz or 2.5 MHz)
RMII_REF_CK as AF
(50 MHz)
1. The MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the SYSCFG_PMC register.
To save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed
on the same GPIO pin.
33.5 Ethernet functional description: MAC 802.3
The IEEE 802.3 International Standard for local area networks (LANs) employs the
CSMA/CD (carrier sense multiple access with collision detection) as the access method.
The Ethernet peripheral consists of a MAC 802.3 (media access control) controller with
media independent interface (MII) and a dedicated DMA controller.
The MAC block implements the LAN CSMA/CD sublayer for the following families of
systems: 10 Mbit/s and 100 Mbit/s of data rates for baseband and broadband systems. Half-
and full-duplex operation modes are supported. The collision detection access method is
applied only to the half-duplex operation mode. The MAC control frame sublayer is
supported.
The MAC sublayer performs the following functions associated with a data link control
procedure:
• Data encapsulation (transmit and receive)
–
–
–
• Media access management
–
–
Ethernet (ETH): media access control (MAC) with DMA controller
Figure
GPIO and AF
controller
50 MHz
GPIO and AF
controller
Framing (frame boundary delimitation, frame synchronization)
Addressing (handling of source and destination addresses)
Error detection
Medium allocation (collision avoidance)
Contention resolution (collision handling)
358.

Figure 358. Clock scheme

25 MHz or 2.5 MHz
Sync. divider
/2 for 100 Mb/s
/20 for 10 Mb/s
25 MHz or 2.5 MHz
RM0090 Rev 18
0 25 MHz MACTXCLK
1 or 2.5 MHz
0 MII
(1)
1 RMII
25 MHz
0 MACRXCLK
or 2.5 MHz
1
HCLK
HCLK
must be greater
than 25 MHz
MAC
TX
AHB
RX
RMII
ai15650
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